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w9751g6jb 8m 4 banks 16 bit ddr2 sdram publication release date: aug. 03, 2010 - 1 - revision a04 table of contents- 1. general des cription ............................................................................................................ .......4 2. features ....................................................................................................................... ....................4 3. key paramet ers ................................................................................................................. ............5 4. ball config uration ............................................................................................................. .........6 5. ball desc ription............................................................................................................... .............7 6. block di agram .................................................................................................................. ..............8 7. functional d escript ion......................................................................................................... .....9 7.1 power-up and initiali zation se quence ........................................................................................... ........9 7.2 mode register and extended m ode registers o peratio n ...................................................................10 7.2.1 mode register set command (mrs) ...............................................................................10 7.2.2 extend mode register set commands (emrs) ..............................................................11 7.2.2.1 extend mode register set command (1), emr (1 )................................................11 7.2.2.2 dll enable/di sable ................................................................................................12 7.2.2.3 extend mode register set command (2), emr (2 )................................................13 7.2.2.4 extend mode register set command (3), emr (3 )................................................14 7.2.3 off-chip driver (ocd) impedance adju stment ................................................................15 7.2.3.1 extended mode register for ocd impedance ad justme nt ....................................16 7.2.3.2 ocd impedance adjust ..........................................................................................16 7.2.3.3 drive mo de .............................................................................................................17 7.2.4 on-die terminat ion (odt )...............................................................................................18 7.2.5 odt related timings .........................................................................................................18 7.2.5.1 mrs command to od t update delay .....................................................................18 7.3 command fu nction............................................................................................................... ..............20 7.3.1 bank activate command..................................................................................................20 7.3.2 read comm and ...............................................................................................................20 7.3.3 write co mmand ...............................................................................................................21 7.3.4 burst read with auto -precharge command .....................................................................21 7.3.5 burst write with auto -precharge command .....................................................................21 7.3.6 precharge all command ..................................................................................................21 7.3.7 self refresh en try comm and .......................................................................................... 21 7.3.8 self refresh ex it comm and ............................................................................................. 22 7.3.9 refresh co mmand ...........................................................................................................22 7.3.10 no-operation command ..................................................................................................23 7.3.11 device desele ct comm and.............................................................................................. 23 7.4 read and write access modes .................................................................................................... .......23 7.4.1 posted cas ....................................................................................................................23 7.4.1.1 examples of posted cas operatio n......................................................................23
w9751g6jb publication release date: aug. 03, 2010 - 2 - revision a04 7.4.2 burst mode op eratio n.......................................................................................................24 7.4.3 burst read mode operatio n...............................................................................................25 7.4.4 burst write mode operatio n ..............................................................................................25 7.4.5 write data mask ...............................................................................................................2 6 7.5 burst in terr upt ................................................................................................................ .....................26 7.6 precharge o peration............................................................................................................ ................27 7.6.1 burst read operation foll owed by pr echarg e.....................................................................27 7.6.2 burst write operation foll owed by pr echarg e ....................................................................27 7.7 auto-precharge operat ion ....................................................................................................... ............27 7.7.1 burst read with au to-prech arge........................................................................................28 7.7.2 burst write with auto-prech arge .......................................................................................28 7.8 refresh o peration.............................................................................................................. .................29 7.9 power down mode................................................................................................................ ..............29 7.9.1 power down entry ...........................................................................................................30 7.9.2 power down exit..............................................................................................................30 7.10 input clock frequenc y change during prec harge power down .............................................................30 8. operation mode ................................................................................................................. ..........31 8.1 command trut h tabl e ............................................................................................................ ............31 8.2 clock enable (cke) truth table fo r synchronous transitio ns............................................................32 8.3 data mask (dm) truth t able..................................................................................................... ..........32 8.4 function trut h tabl e ........................................................................................................... ................33 8.5 simplified st ated dia gram ...................................................................................................... .............36 9. electrical chara cteristi cs ...................................................................................................37 9.1 absolute maxi mum ra tings....................................................................................................... ..........37 9.2 operating temperat ure cond ition................................................................................................ .......37 9.3 recommended dc operat ing condit ions ...........................................................................................3 7 9.4 odt dc electrical characteri stics .............................................................................................. ........38 9.5 input dc lo gic lev el........................................................................................................... ................38 9.6 input ac log ic lev el ........................................................................................................... ................38 9.7 capacit ance .................................................................................................................... ....................39 9.8 leakage and output buffe r characte ristics ...................................................................................... ..39 9.9 dc characte ristics ............................................................................................................. .................40 9.10 idd measurement te st para meters................................................................................................ ....42 9.11 ac characte ristics ............................................................................................................. .................43 9.11.1 ac characteristics and operating condition for - 18 speed grade ...................................43 9.11.2 ac characteristics and operating co ndition for -25/25 i/-3 speed grade .........................45 9.12 ac input test condit ions ....................................................................................................... .............65 9.13 differential input/out put ac logi c leve ls ...................................................................................... .....65 9.14 ac overshoot / undersh oot specif ication ........................................................................................ ...66 9.14.1 ac overshoot / undershoot specificati on for address and control pi ns: ........................66 9.14.2 ac overshoot / undershoot s pecification for clock, data, strobe and mask pins:..........66 10. timing w aveforms ............................................................................................................... ........67 10.1 command inpu t timing........................................................................................................... ............67
w9751g6jb publication release date: aug. 03, 2010 - 3 - revision a04 10.2 timing of the clk sign als...................................................................................................... .............67 10.3 odt timing for acti ve/standb y mode............................................................................................. ....68 10.4 odt timing for po wer down mode ................................................................................................. ...68 10.5 odt timing mode switch at ent ering power do wn m ode .................................................................... 69 10.6 odt timing mode switch at exiting power down mode ......................................................................70 10.7 data output (r ead) ti ming ...................................................................................................... ..............71 10.8 burst read operation: rl=5 (al=2, cl=3 , bl=4) ................................................................................71 10.9 data input (w rite) ti ming ...................................................................................................... ................72 10.10 burst write operation: rl=5 (al=2, cl=3, wl =4, bl=4 )...........................................................72 10.11 seamless burst read operation: rl = 5 ( al = 2, and cl = 3, bl = 4) ......................................73 10.12 seamless burst write operation: rl = 5 ( wl = 4, bl = 4).........................................................73 10.13 burst read interrupt timing: rl =3 (cl=3, al =0, bl=8 ) .............................................................74 10.14 burst write interrupt timing: rl=3 (cl=3, al=0, wl=2, bl=8) ..................................................74 10.15 write operation with data ma sk: wl=3, al=0 , bl=4) ...............................................................75 10.16 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=4, trtp 2clks) ............76 10.17 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=8, trtp 2clks) ............76 10.18 burst read operation followed by precharge: rl=5 (al=2, cl=3, bl=4, trtp 2clks) ............77 10.19 burst read operation followed by precharge: rl=6 (al=2, cl=4, bl=4, trtp 2clks) ............77 10.20 burst read operation followed by precharge: rl=4 (al=0, cl=4, bl =8, trtp > 2clks) ............78 10.21 burst write operation followed by precharge: wl = (rl-1) = 3 ..................................................78 10.22 burst write operation followed by precharge: wl = (rl-1) = 4 ..................................................79 10.23 burst read operation with auto-prechar ge: rl=4 (al=1, cl=3, bl=8, trtp 2clks) ...............79 10.24 burst read operation with auto-precharge: rl =4 (al=1, cl=3, bl=4 , trtp > 2clks) ...............80 10.25 burst read with auto-precharge followed by an ac tivation to the same bank (trc limit): rl=5 (al=2, cl=3, internal trcd=3, bl=4, trtp 2cl ks).......................................................................................80 10.26 burst read with auto-precharge followed by an ac tivation to the same bank (trp limit): rl=5 (al=2, cl=3, internal trcd=3, bl=4, trtp 2cl ks).......................................................................................81 10.27 burst write with auto-precharge (trc limit): wl=2, wr=2 , bl=4, trp=3.................................81 10.28 burst write with auto-precharge (wr + trp limit): wl=4, wr =2, bl=4, trp=3 .......................82 10.29 self refres h timi ng ............................................................................................................ .......82 10.30 active power down mode en try and exit timi ng....................................................................... 83 10.31 precharged power down mode entry and exit timi ng ..............................................................83 10.32 clock frequency change in pr echarge power do wn mode ........................................................84 11. package specif ication .......................................................................................................... ....85 package outline wbga-84 (8x12.5 mm 2 ).......................................................................................................85 12. revision history ............................................................................................................... ...........86
w9751g6jb publication release date: aug. 03, 2010 - 4 - revision a04 1. general description the w9751g6jb is a 512m bits ddr2 sdram, organized as 8,388,608 words 4 banks 16 bits. this device achieves high speed transfer rates up to 1066mb/sec/pin (ddr2-1066) for general applications. w9751g6jb is sorted into the following speed grades: -18, -25, 25i and -3. the -18 is compliant to the ddr2-1066 (7-7-7) specification. th e -25/25i are compliant to the dd r2-800 (5-5-5) or ddr2-800 (6-6-6) specification (the 25i industrial grade which is guaranteed to support -40c t case 95c). the -3 is compliant to the ddr2-667 (5-5-5) specification. all of the control and address inputs are synchronized with a pair of exte rnally supplied differential clocks. inputs are latched at the cross point of differential clocks (clk rising and clk falling). all i/os are synchronized with a single ended dqs or differential dqs- dqs pair in a source synchronous fashion. 2. features z power supply: v dd , v ddq = 1.8 v 0.1 v z double data rate architecture: two data transfers per clock cycle z cas latency: 3, 4, 5, 6 and 7 z burst length: 4 and 8 z bi-directional, differential data strobes (dqs and dqs ) are transmitted / received with data z edge-aligned with read data and center-aligned with write data z dll aligns dq and dqs transitions with clock z differential clock inputs (clk and clk ) z data masks (dm) for write data z commands entered on each positive clk edge, data and data mask are referenced to both edges of dqs z posted cas programmable additive latency supported to make command and data bus efficiency z read latency = additive latency plus cas latency (rl = al + cl) z off-chip-driver impedance adjustment (ocd) and on-d ie-termination (odt) for better signal quality z auto-precharge operation for read and write bursts z auto refresh and self refresh modes z precharged power down and active power down z write data mask z write latency = read latency - 1 (wl = rl - 1) z interface: sstl_18 z packaged in wbga 84 ball (8x12.5 mm 2 ), using lead free materials with rohs compliant
w9751g6jb publication release date: aug. 03, 2010 - 5 - revision a04 3. key parameters speed grade ddr2-1066 ddr2-800 ddr2-667 bin(cl-trcd-trp) 7-7- 7 5-5-5/6-6-6 5-5-5 sym. part number extension -18 -25/25i -3 min. 1.875 ns ? ? @cl = 7 max. 7.5 ns ? ? min. 2.5 ns 2.5 ns ? @cl = 6 max. 7.5 ns 8 ns ? min. 3 ns 2.5 ns 3 ns @cl = 5 max. 7.5 ns 8 ns 8 ns min. 3.75 ns 3.75 ns 3.75 ns @cl = 4 max. 7.5 ns 8 ns 8 ns min. ? 5 ns 5 ns t ck(avg) average clock period @cl = 3 max. ? 8 ns 8 ns t rcd active to read/write command delay time min. 13.125 ns 12.5 ns 15 ns t rp precharge to active command period min. 13.125 ns 12.5 ns 15 ns t rc active to ref/active command period min. 53.125 ns 52.5 ns 55 ns t ras active to precharge command period min. 40 ns 40 ns 40 ns i dd0 operating current ma x. 105 ma 90 ma 80 ma i dd1 operation current (single bank) max. 115ma 100 ma 90 ma i dd4r operating burst read current max. 165 ma 140 ma 125 ma i dd4w operating burst write curre nt max. 200 ma 165 ma 150 ma i dd5b burst refresh current max. 105 ma 95 ma 90 ma i dd6 self refresh current (t case Q 85 c ) max. 6 ma 6 ma 6 ma i dd7 operating bank interleave read current max. 245 ma 200 ma 180 ma
w9751g6jb publication release date: aug. 03, 2010 - 6 - revision a04 4. ball configuration 123456789 a b c d e f g h j k l vssq udqs vddq ldqs vddq cas a2 a6 udqs vssq dq8 vssq dq0 clk a0 a4 clk cs vddq vddq dq7 vdd odt vdd dq14 vddq dq12 nc vddl nc vssq dq9 vssq a3 cke ba0 ba1 we dq3 ldm vss dq11 vddq vss udm vdd dq6 vddq dq4 vss vdd a12 nc nc nc a11 a8 a9 a7 a5 a1 a10/ap vss vref dq1 vssq vddq vssq nc vssq ldqs vssq dq10 dq15 dq13 vddq vddq dq5 vdd vss m n p r vssq dq2 vssdl ras
w9751g6jb publication release date: aug. 03, 2010 - 7 - revision a04 5. ball description ball number symbol function description m8,m3,m7,n2,n8,n3 ,n7,p2,p8,p3,m2,p7 ,r2 a0 ? a12 address provide the row address for active commands, and the column address and auto-precharge bit for read/write commands to select one location out of the memory array in the respective bank. row address: a0 ? a12. column address: a0 ? a9. (a10 is used for auto-precharge) l2,l3 ba0 ? ba1 bank select ba0 ? ba1 define to which bank an active, read, write or precharge command is being applied. g8,g2,h7,h3,h1,h9 ,f1,f9,c8,c2,d7,d3, d1,d9,b1,b9 dq0 ? dq15 data input / output bi-directional data bus. k9 odt on die termination control odt (registered high) enables termi nation resistance internal to the ddr2 sdram. f7,e8 ldqs, ldqs low data strobe data strobe for lower byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. ldqs corresponds to the data on dq0 ? dq7. ldqs is only used when differential data strobe mode is enabled via the control bit at emr (1)[a10 emrs command]. b7,a8 udqs, udqs up data strobe data strobe for upper byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with write data. udqs corresponds to the data on dq8 ? dq15. udqs is only used when differential data strobe mode is enabled via the control bit at emr (1)[a10 emrs command]. l8 cs chip select all commands are masked when cs is registered high . cs provides for external bank selection on systems with multiple ranks. cs is considered part of the command code. k7,l7,k3 ras , cas , we command inputs ras , cas and we (along with cs ) define the command being entered. b3,f3 udm ldm input data mask dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. j8,k8 clk, clk differential clock inputs clk and clk are differential clock inputs. all address and control input signals are sampled on the cr ossing of the positive edge of clk and negative edge of clk . output (read) data is referenced to the crossings of clk and clk (both directions of crossing). k2 cke clock enable cke (registered high) activates and cke (registered low) deactivates clocking circui try on the ddr2 sdram. j2 v ref reference voltage v ref is reference voltage for inputs. a1,e1,j9,m9,r1 v dd power supply power supply: 1.8v 0.1v. a3,e3,j3,n1,p9 v ss ground ground. a9,c1,c3,c7,c9,e9, g1,g3,g7,g9 v ddq dq power supply dq power supply: 1.8v 0.1v. a7,b2,b8,d2,d8,e7, f2,f8,h2,h8 v ssq dq ground dq ground. isolated on th e device for improved noise immunity. a2,e2,l1,r3,r7,r8 nc no connection no connection. j7 v ssdl dll ground dll ground. j1 v ddl dll power supply dll power supply: 1.8v 0.1v.
w9751g6jb publication release date: aug. 03, 2010 - 8 - revision a04 6. block diagram cke a10 dll clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 8192 * 1024 * 16 row decoder row decoder row decoder row decoder a0 a9 a11 a12 ba1 ba0 cs ras cas we clk clk prefetch register odt control dq0 | dq15 ldqs ldqs udqs udqs ldm udm odt
w9751g6jb publication release date: aug. 03, 2010 - 9 - revision a04 7. functional description 7.1 power-up and initialization sequence ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power-up and initialization. 1. apply power and attempt to maintain cke below 0.2 v ddq and odt *1 at a low state (all other inputs may be undefined.) either one of the follo wing sequence is required for power-up. a. the v dd voltage ramp time must be no greater than 200 ms from when v dd ramps from 300 mv to v dd min; and during the v dd voltage ramp, |v dd -v ddq | Q 0.3 volts. z v dd , v ddl and v ddq are driven from a single power converter output z v tt is limited to 0.95v max z v ref *2 tracks v ddq /2 z v ddq R v ref must be met at all times b. voltage levels at i/os and outputs must be less than v ddq during voltage ramp time to avoid dram latch-up. during the ramping of the supply voltages, v dd R v ddl R v ddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete. z apply v dd /v ddl *3 before or at the same time as v ddq z apply v ddq *4 before or at the same time as v tt z v ref *2 tracks v ddq /2 z v ddq R v ref must be met at all times. 2. start clock and maintain stable condition for 200 s (min.). 3. after stable power and clock (clk, clk ), apply nop or deselect and take cke high. 4. wait minimum of 400 ns then issue precharge all command. nop or deselect applied during 400 ns period. 5. issue an emrs command to emr (2). (to i ssue emrs command to emr (2), provide low to ba0, high to ba1.) 6. issue an emrs command to emr (3). (to iss ue emrs command to emr (3), provide high to ba0 and ba1.) 7. issue emrs to enable dll. (to issue dll e nable command, provide low to a0, high to ba0 and low to ba1. and a9=a8=a7=low must be used when issuing this command.) 8. issue a mode register set command for dll re set. (to issue dll reset command, provide high to a8 and low to ba0 and ba1.) 9. issue a precharge all command. 10. issue 2 or more auto refresh commands. 11. issue a mrs command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr (1) to set ocd calibration default (a9=a8=a7=high) followed by emrs to emr (1) to exit ocd calibration mode (a9=a8=a7=low) must be issued with ot her operating parameters of emr(1). 13. the ddr2 sdram is now ready for normal operation.
w9751g6jb publication release date: aug. 03, 2010 - 10 - revision a04 notes: 1. to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. 2. v ref must be within 300 mv with respect to v ddq /2 during supply ramp time. 3. v dd /v ddl voltage ramp time must be no greater than 200 ms from when v dd ramps from 300 mv to v dd min. 4. the v ddq voltage ramp time from when v dd min is achieved on v dd to when v ddq min is achieved on v ddq must be no greater than 500 ms t ch t cl t is t is 400ns nop pre all emrs mrs pre all ref mrs ref emrs emrs any cmd t rp t mrd t mrd t rp t rfc t rfc t oit follow ocd flow chart ocd cal. mode exit ocd default min 200 cycle dll reset dll enable clk clk cke command odt t mrd figure 1 ? initialization sequence after power-up 7.2 mode register and extende d mode registers operation for application flexibility, burst le ngth, burst type, cas latency, dll reset function, write recovery time (wr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, driv er impedance, additive cas latency, odt (on die termination), single-ended strobe and ocd (off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) or ext ended mode registers emr (1), emr (2) and emr (3) can be altered by re-executing the mrs or emrs command s. even if the user chooses to modify only a subset of the mr or emr (1), emr (2) and emr (3) variables, all variables within the addressed register must be redefined when t he mrs or emrs commands are issued. mrs, emrs and reset dll do not affect array content s, which mean re-initialization including those can be executed at any time after powe r-up without affecting array contents. 7.2.1 mode register set command (mrs) ( cs = "l", ras = "l", cas = "l", we = "l", ba0 = "l", ba1 = "l", a0 to a12 = register data) the mode register stores the dat a for controlling the va rious operating modes of ddr2 sdram. it programs cas latency, burst length, burst sequence, test mode, dll reset, write recovery (wr) and various vendor specific options to make ddr2 sd ram useful for various applications. the default value in the mode register after power-up is no t defined, therefore the mode register must be programmed during initialization for proper operation. the ddr2 sdram should be in all bank precharge st ate with cke already high prior to writing into the mode register. the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. the mode register is divided into various fields depending on functionality. burst length is defined by a[2:0] with options of 4 and 8 bit burst lengths . the burst length decodes are compatible with ddr
w9751g6jb publication release date: aug. 03, 2010 - 11 - revision a04 sdram. burst address sequence type is defined by a3 , cas latency is defined by a[6:4]. the ddr2 does not support half clock latency mode. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. write recove ry time wr is defined by a[11:9]. refer to the table for specific codes. ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pd wr dll bt cas latency burst length tm a8 0 1 dll reset no yes ba1 ba0 00 01 10 11 mrs mode mr emr (1) emr (2) emr (3) a12 1 0 active power down exit time fast exit (use t xard ) slow exit (use t xards ) burst length address field mode register write recovery for auto-precharge cas latency a6 0 0 0 0 1 1 1 1 a5 0 0 1 1 0 0 1 1 a4 0 1 0 1 0 1 1 0 latency reserved 3 4 5 7 6 reserved reserved a2 0 0 a1 1 1 a0 0 1 bl 4 8 a11 0 0 0 0 1 1 1 1 a10 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 1 0 wr * reserved 2 3 4 5 6 8 7 a7 0 1 mode normal test a3 0 1 burst type sequential interleave 0 ddr2-667 ddr2-800 ddr2-1066 ddr2-800 ddr2-1066 ddr2-667 ba1 0 note: 1. wr (write recovery for auto-precharge) min is determined by tck(avg) max and wr max is determined by tck(avg) min. wr[cycles] = ru{ twr[ns] / tck(avg)[ns] }, where ru stands fo r round up. the mode register must be programmed to this value. this is also used with trp to determine tdal. figure 2 ? mode register set (mrs) 7.2.2 extend mode register set commands (emrs) 7.2.2.1 extend mode register set command (1), emr (1) ( cs = "l", ras = "l", cas = "l", we = "l", ba0 = "h", ba1 = "l", a0 to a12 = register data) the extended mode register (1) st ores the data for enabling or disa bling the dll, output driver strength, additive latency, odt, dqs disable, ocd program. the default value of the extended mode register (1) is not defined, th erefore the extended mode register (1) must be programmed during initialization for proper operation. the ddr2 sd ram should be in all bank precharge with cke already high prior to writing into the extended mode register (1). the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the ext ended mode register (1). extended mode register (1) contents can be ch anged using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a re duced strength output driver . a[5:3] determines the additive latency, a[9:7] are used for ocd control, a10 is used for dqs disable. a2 and a6 are used for odt setting.
w9751g6jb publication release date: aug. 03, 2010 - 12 - revision a04 7.2.2.2 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow ti me for the internal clock to be synchronized with the external clock. failing to wait for synchr onization to occur may result in a violation of the t ac or t dqsck parameters . ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 ocd program bt rtt address field extended mode register (1) ba1 ba0 mrs mode 0 0 0 0 1 1 11 mr emr (1) emr (2) emr (3) a6 a2 0 0 0 0 1 1 11 wr additive latency qoff 0* 1 dqs rtt d.i.c dll rtt (nominal) odt disabled 75 ohm 150 ohm 50 ohm* 2 0 a0 1 dll enable enable disable ocd calibration program ocd calibration mode exit; matain setting adjust mode* 3 ocd calibration default* 4 drive (1) drive (0) a9 a8 a7 1 000 11 1 1 1 00 0 0 0 0 driver impedance adjustment a12 1 0 output buffer enabled qoff (optional)* 5 output buffer disabled a10 1 0 dqs enable disable a10 (dqs enable) 0 (enable) 1 (disable) strobe function matrix dqs dqs dqs dqs dqs hi-z output driver impedance control reduced normal a1 0 1 a5 0 0 0 0 1 1 1 1 a4 0 0 1 1 0 0 1 1 a3 0 1 0 1 0 1 1 0 latency 0 3 4 reserved 1 2 output driver impedance control driver size 100% 60% additive latency 5 6 ddr2-/667/800 ddr2-1066 notes: 1. a11 default is ?0 ? rdqs disabled . 2. optional for ddr2-667, mandatory for ddr2-800 and ddr2-1066. 3. when adjust mode is issued, al from previously set value must be applied. 4. after setting to default, ocd calibration mode needs to be ex ited by setting a9-a7 to 000. refer to the section 7.2.3 for detailed information. 5. output disabled - dqs, ldqs, ldqs , udqs, udqs . this feature is used in conjunction with dimm i dd measurements when i ddq is not desired to be included. figure 3 ? emr (1)
w9751g6jb publication release date: aug. 03, 2010 - 13 - revision a04 7.2.2.3 extend mode register set command (2), emr (2) ( cs = "l", ras = "l", cas = "l", we = "l", ba0 = "l", ba1 = "h", a0 to a12 = register data) the extended mode register (2) controls refresh re lated features. the default value of the extended mode register (2) is not defined, th erefore the extended mode register (2) must be programmed during initialization for proper operation. the ddr2 sdram should be in all bank precharge st ate with cke already high prior to writing into the extended mode register (2). the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a12a11a10a9a8a7a6a5a4a3a2a1a0 0 self 0* 1 address field extended mode register (2) 0* 1 a7 1 0 disable high temperature self refresh rate enable enable* 2 ba0 1 ba1 ba0 mrs mode 0 0 0 0 1 1 11 mrs emr (1) emr (2) emr (3) ba1 notes: 1. the rest bits in emr (2) is reserved for future use and a ll bits in emr (2) except a7, ba0 and ba1 must be programmed to 0 when setting the extended mode register (2) during initialization. 2. when dram is operated at 85 c < tcase 95 c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. figure 4 ? emr (2)
w9751g6jb publication release date: aug. 03, 2010 - 14 - revision a04 7.2.2.4 extend mode register set command (3), emr (3) ( cs = "l", ras = "l", cas = "l", we = "l", ba0 = "h", ba1 = "h", a0 to a12 = register data) no function is defined in extended mode register (3 ). the default value of the emr (3) is not defined, therefore the emr (3) must be programmed du ring initialization for proper operation. ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 11 address field extended mode register (3) 0* 1 note: 1. all bits in emr (3) except ba0 and ba1 are reserved for future use and must be set to 0 when programming the emr (3). figure 5 ? emr (3)
w9751g6jb publication release date: aug. 03, 2010 - 15 - revision a04 7.2.3 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart in figure 6 is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) shoul d be carefully controlled depending on system environment. start all ok all mr shoud be programmed before enteri ng ocd impedance adjustment and odt should be carefully controlled depending on system environment emrs: drive(0) dq &dqs low; dqs high emrs: ocd calibration mode exit test need calibration emrs: ocd calibration mode exit emrs: enter adjust mode bl=4 code input to all dqs inc, dec or nop emrs: ocd calibration mode exit all ok emrs: drive(1) dq &dqs high; dqs low test need calibration emrs: ocd calibration mode exit emrs: enter adjust mode bl=4 code input to all dqs inc, dec or nop emrs: ocd calibration mode exit emrs: ocd calibration mode exit end figure 6 ? ocd impedance adjustment flow chart
w9751g6jb publication release date: aug. 03, 2010 - 16 - revision a04 7.2.3.1 extended mode register for ocd impedance adjustment ocd impedance adjustment can be done using the fo llowing emrs mode. in drive mode all outputs are driven out by ddr2 sdram. in drive (1) mode, all dq, dqs signals are driven high and all dqs signals are driven low. in drive (0) mode, all dq, dqs signals are driven low and all dqs signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics ha ve a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. ocd app lies only to normal full strength output drive setting defined by emr (1) and if reduced strength is set, ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used , ocd default output driv er characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust ocd characterist ics must specify a[9:7] as ?000? in order to maintain the default or calibrated value. table 1 ? ocd drive mode program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive (1) dq, dqs high and dqs low 0 1 0 drive (0) dq, dqs low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default 7.2.3.2 ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4 bit burst code to ddr2 sdram as in table 2. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst co de to all dqs at the same time. d t0 in table 2 means all dq bits at bit time 0, d t1 at bit time 1, and so forth. the driver output impedance is adjusted for a ll ddr2 sdram dqs simultaneously and after ocd calibration, all dqs and dqs?s of a given ddr2 sdram will be adjus ted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the 16 step range. when adjust mode command is issued, al from previously set value must be applied. table 2 ? ocd adjust mode program 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0 0 0 0 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved
w9751g6jb publication release date: aug. 03, 2010 - 17 - revision a04 for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds /t dh should be met as shown in figure 7. for input data pattern for adjustment, d t0 - d t3 is a fixed order and is not affected by burst type (i.e., sequential or interleave). ocd adjust mode ocd calibration mode exit wr wl dqs tds tdh dt0 emrs(1) nopnopnopnopnopnop clk dqs_in cmd dq_in dm nop emrs nop nop nop nop nop nop emrs clk dt1 dt2 dt3 figure 7 ? ocd adjust mode 7.2.3.3 drive mode drive mode, both drive (1) and drive (0), is used for controllers to meas ure ddr2 sdram driver impedance. in this mode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command as shown in figure 8. enter drive mode ocd calibration mode exit emrs emrs nop nop nop nop nop nop nop clk dqs dqs cmd dq t oit t oit dqs high for drive (1) dqs low for drive (0) dqs high & dqs low for drive (1), dqs low & dqs high for drive (0) clk hi-z figure 8 ? ocd drive mode
w9751g6jb publication release date: aug. 03, 2010 - 18 - revision a04 7.2.4 on-die termination (odt) on-die termination (odt) is a new feature on ddr2 components that allows a dram to turn on/off termination resistance for each dq, udqs/ udqs , ldqs/ ldqs , udm and ldm signal via the odt control pin. udqs and ldqs are terminated only when enabled in the emr (1) by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termi nation resistance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self refresh mode. (example timing waveforms refer to 10.3, 10.4 odt timing for active/standby/power down mode and 10.5, 10.6 od t timing mode switch at entering/exiting power down mode diagram in chapter 10) dram input buffer input pin v ddq sw1 rval3 v ddq v ddq sw2 sw3 rval1 rval2 rval1 rval2 rval3 sw1 sw2 sw3 v ssq v ssq v ssq switch (sw1, sw2, sw3) is enabled by odt pin. selection among sw1, sw2, and sw3 is determined by ?rtt (nominal)? in emr (1). termination included on all dqs, dm, dqs, dqs pins. figure 9 ? functional representation of odt 7.2.5 odt related timings 7.2.5.1 mrs command to odt update delay during normal operation the value of the effective termination resistance can be changed with an emrs command. the update of the rtt setting is done between t mod ,min and t mod ,max, and cke must remain high for the entire duration of t mod window for proper operation. the timings are shown in the following timing diagram.
w9751g6jb publication release date: aug. 03, 2010 - 19 - revision a04 cmd clk clk odt rtt updating new setting t is t mod,min t mod,max t aofd emrs nop nop nop nop nop old setting 1) emrs command directed to emr(1), which updates th e information in emr(1)[a6, a2], i.e. rtt (nominal). 2) setting? in this diagram is th e register and i/o se tting, not what is measured from outside. figure 10 ? odt update delay timing - t mod however, to prevent any impedance glitch on the channel, the following conditions must be met. z t aofd must be met before issuing the emrs command. z odt must remain low for the entire duration of t mod window, until t mod ,max is met. now the odt is ready for normal operation with the new setting, and the odt signal may be raised again to turned on the odt. following timing diagram shows the proper rtt update procedure. clk clk cmd odt rtt old setting new setting t aond t is t mod,max t aofd emrs nop nop nop nop nop 1) emrs command directed to emr(1), which updates the information in emr(1)[a6,a2], i.e. rtt (nominal). 2) setting in this diagram is what is measured from outside. figure 11 ? odt update delay timing - t mod , as measured from outside
w9751g6jb publication release date: aug. 03, 2010 - 20 - revision a04 7.3 command function 7.3.1 bank activate command ( cs = "l", ras = "l", cas = "h", we = "h", ba0, ba1 = bank, a0 to a12 be row address) the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command on the following clock cycle. if a read/write command is issued to a bank that has not satisfied the t rcdmin specification, then additive latency must be programmed into the device to delay when the read/write command is internally issued to the device. the additive latency value must be chosen to assure t rcdmin is satisfied. additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between bank activate commands is t rrd . figure 12 ? bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2, t ccd = 2 7.3.2 read command ( cs = "l", ras = "h", cas = "l", we = "h", ba0, ba1 = bank, a10 = "l", a0 to a9 = column address) the read command is used to initiate a burst re ad access to an active row. the value on ba0, ba1 inputs selects the bank, and the a0 to a9 address in puts determine the starting column address. the address input a10 determines whether or not auto-p recharge is used. if auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto-precharge is not selected, the row will remain open for subsequent accesses.
w9751g6jb publication release date: aug. 03, 2010 - 21 - revision a04 7.3.3 write command ( cs = "l", ras = "h", cas = "l", we = "l", ba0, ba1 = bank, a10 = "l", a0 to a9 = column address) the write command is used to initiate a burst write access to an active row. the value on ba0, ba1 inputs selects the bank, and the a0 to a9 address in puts determine the starting column address. the address input a10 determines whether or not auto-p recharge is used. if auto-precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto-precharge is not selected, the row will remain open for subsequent accesses. 7.3.4 burst read with auto-precharge command ( cs = "l", ras = "h", cas ="l", we = "h", ba0, ba1 = bank, a10 = "h", a0 to a9 = column address) if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later than the read with ap command if t ras( min) and t rtp (min) are satisfied. 7.3.5 burst write with auto-precharge command ( cs = "l", ras = "h", cas = "l", we = "l", ba0, ba1 = bank, a10 = "h", a0 to a9 = column address) if a10 is high when a write command is issued, t he write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge ope ration after the completion of the burst write plus write recovery time (wr) programmed in the mode register. 7.3.6 precharge all command ( cs = "l", ras = "l", cas = "h", we = "l", ba0, ba1 = don?t care, a10 = "h", a0 to a9 and a11 to a12 = don?t care) the precharge all command precharge all banks simu ltaneously. then all banks are switched to the idle state. 7.3.7 self refresh entry command ( cs = "l", ras = "l", cas = "l", we = "h", cke = "l", ba0, ba1 , a0 to a12 = don?t care) the self refresh command can be used to retain dat a, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 s dram retains data without external clocking. the ddr2 sdram device has a built-in timer to acco mmodate self refresh operation. odt must be turned off before issuing self refresh command, by either driving odt pin low or using an emrs command. once the command is registered, cke mu st be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode, all of the external signals except cke, are ?don?t care?. the clock is internally disabled during self refresh operation to save power. the user may change the external clock frequency or halt the external clo ck one clock after self refresh entry is registered; however, the clock must be restar ted and stable before the device c an exit self refresh operation.
w9751g6jb publication release date: aug. 03, 2010 - 22 - revision a04 7.3.8 self refresh exit command (cke = "h", cs = "h" or cke = "h", cs = "l", ras = "h", cas = "h", we = "h", ba0, ba1, a0 to a12 = don?t care) the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refr esh exit is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high fo r the entire self refresh exit period t xsrd for proper operation except for self refresh re-entry. upon exit from self refresh, the ddr2 sdram ca n be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command (refresh period of t rfc ). nop or deselect commands must be registered on each positive cloc k edge during the self refresh exit interval t xsnr . odt should be turned off during t xsrd . the use of self refresh mode introduces the possibil ity that an internally timed refresh event can be missed when cke is raised for exit from self re fresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extr a auto refresh command before it is put back into self refresh mode. 7.3.9 refresh command ( cs = "l", ras = "l", cas = "l", we = "h", cke = "h", ba0, ba1 , a0 to a12 = don?t care) refresh is used during normal operation of the ddr2 sdram. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the intern al refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the ddr2 sdram requires auto refresh cycles at an average periodic interval of t refi (max.) . when the refresh cycle has completed, all banks of the ddr2 sdram will be in the precharged (idle) state. a delay between the auto refresh comm and (ref) and the next activate command or subsequent auto refresh command must be greater th an or equal to the auto refresh cycle time (t rfc ). to allow for improved efficiency in scheduling and swit ching between tasks, some flexibility in the absolute refresh interval is provided. a maximu m of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum abs olute interval between any refresh command and the next refresh command is 9 x t refi . t0 t1 t2 t3 clk/clk cke cmd t rp t rfc t rfc nop nop nop any ref ref precharge "high" tm tn tn + 1 figure 13 ? refresh command
w9751g6jb publication release date: aug. 03, 2010 - 23 - revision a04 7.3.10 no-operation command ( cs = "l", ras = "h", cas = "h", we = "h", cke, ba0, ba1, a0 to a12 = don?t care) the no-operation command simply performs no operation (same command as device deselect). 7.3.11 device deselect command ( cs = "h", ras , cas , we , cke, ba0, ba1, a0 to a12 = don?t care) the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no-operation command. 7.4 read and write access modes the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundar y of the burst cycle is strictly restricted to specific segments of the page length. the 8 mbit x 16 i/o x 4 bank chip has a page length of 1024 bits (defined by ca0 to ca9) * . the page length of 1024 is divided into 256 or 128 uniqu ely addressable boundary segments depending on burst length, 256 for 4 bit burst, 128 for 8 bit burst re spectively. a 4-bit or 8-bit burst operation will occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the device during the read or write command (ca0 to ca9). the second, third and fourth access will also occur within this group segment. however, t he burst order is a functi on of the starting address, and the burst sequence. a new burst access must not interr upt the previous 4 bit burst operat ion in case of bl = 4 setting. however, in case of bl = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, t he other writes interrupted by a write with 4 bit burst boundary respectively. the minimum cas to cas delay is defined by t ccd , and is a minimum of 2 clocks for read or write cycles. note: page length is a function of i/o organization and column addressing 8m bits 16 organization (ca0 to ca9); page length = 1024 bits 7.4.1 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas read or write command to be issued immediately after the ras bank activate command (or any time during the ras - cas -delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas latency (cl). therefore if a user choose s to issue a read/write command before the t rcdmin , then al (greater than 0) must be written into the emr (1). the write latency (wl) is always defined as rl -1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl = al + cl). read or write ope rations using al allow seamless bursts. (example timing waveforms refer to 10.11 and 10.12 seamless burs t read/write operation diagram in chapter 10) 7.4.1.1 examples of posted cas operation examples of a read followed by a write to the sa me bank where al = 2 and where al = 0 are shown in figures 14 and 15, respectively.
w9751g6jb publication release date: aug. 03, 2010 - 24 - revision a04 cmd 123 45 6 789101112 0 -1 clk /clk dqs/dqs dq al=2 cl=3 wl=rl-1=4 t rcd rl=al+cl=5 dout0 din0 active a-bank read a-bank write a-bank din1 din2 din3 dout1 dout2 dout3 [al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4, bl = 4] figure 14 ? example 1: read followed by a write to the same bank, where al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4, bl = 4 123456 7891011 12 0 -1 cl=3 wl=rl-1=2 t rcd rl=al+cl=3 al=0 cmd clk/clk dq dout0 dout1 dout2 dout3 din0 din1 din2 din3 write a-bank read a-bank active a-bank dqs/dqs al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4] figure 15 ? example 2: read followed by a write to the same bank, where al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4 7.4.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burs t length is programmable and defined by mr a[2:0]. the burst type, either sequential or interleaved, is programmabl e and defined by mr [a3]. seamless burst read or write oper ations are supported. unlike ddr1 devices, interruption of a burst read or writes cycle during bl = 4 mode operation is prohibited. however in case of bl = 8 mode, interrup tion of a burst read or write operation is limited to two cases, reads interrupted by a read , or writes interrupted by a write. (example timing waveforms refer to 10.13 and 10.14 burst read and write interrupt timing diagram in chapter 10)
w9751g6jb publication release date: aug. 03, 2010 - 25 - revision a04 therefore the burst stop command is not supported on ddr2 sdram devices. table 3 ? burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 7.4.3 burst read mode operation burst read is initiated with a read command. the address inputs determine the starting column address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data st robe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a so urce synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register emr (1). (example timing waveforms refer to 10.7 and 10.8 data output (read) timing and burst read operation diagram in chapter 10) 7.4.4 burst write mode operation burst write is initiated with a write command. the address inputs determine the starting column address for the burst. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1); and is the number of clocks of delay that are required fr om the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe signal (dqs) should be driven low (preamble) nominally half clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for each posit ive dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (wr). (example timing waveforms refer to 10.9 and 10.10 data input (write) timing and burst write operation diagram in chapter 10)
w9751g6jb publication release date: aug. 03, 2010 - 26 - revision a04 7.4.5 write data mask one write data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdram, consistent with the implementation on ddr1 sdram. it has identical timings on write operations as the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to insure matched system timing. dm is not used during read cycles. (example timing waveform refer to 10.15 write operation with data mask diagram in chapter 10) 7.5 burst interrupt read or write burst interruption is prohibited for burst length of 4 a nd only allowed for burst length of 8 under the following conditions: 1. read burst of 8 can only be interrupted by another read command. read burst interruption by write or precharge command is prohibited. 2. write burst of 8 can only be interrupted by another write command. write burst interruption by read or precharge command is prohibited. 3. read burst interrupt must oc cur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two cl ocks after the previous write command. any other write burst interrupt timings are prohibited. 5. read or write burst interruption is allo wed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to interrupt. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst le ngth set in the mode register. they are not referenced to the actual burst. for example below: z minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (whi ch is shorter because of interrupt). z minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not from the end of the actual burst end. (example timing waveforms refer to 10.13 and 10.14 burst read and write interrupt timing diagram in chapter 10)
w9751g6jb publication release date: aug. 03, 2010 - 27 - revision a04 7.6 precharge operation the precharge command is used to precharge or close a bank that has been activated. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba0 and ba1 are used to define which bank to precharge when the command is issued. table 4 ? bank selection for precharge by address bits a10 ba1 ba0 precharge bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks 7.6.1 burst read operation followed by precharge minimum read to precharge command spacing to the same bank = al + bl/2 + max(rtp, 2) - 2 clks for the earliest possible prechar ge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 + max(rtp, 2) - 2 clocks? after a read command. a new bank active (command) may be issued to the same bank after the ras precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time from al + 2 clocks after the read to the precharge command. (example timing waveforms refer to 10.16 to 10.20 burst read operation followed by precharge diagram in chapter 10) 7.6.2 burst write operation followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 clks + t wr for write cycles, a delay must be satisfied from th e completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay. (example timing waveforms refer to 10.21 to 10.22 burst write operation followed by precharge diagram in chapter 10) 7.7 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible mo ment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains acti ve at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is engaged. during auto-precharge, a read command will ex ecute as normal with the exception that the active bank will begin to precharge on the rising edge which is c as latency (cl) clock cycles before the end of the read burst.
w9751g6jb publication release date: aug. 03, 2010 - 28 - revision a04 auto-precharge is also implemented during write commands. the precharge operation engaged by the auto-precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improvi ng system performance for random data access. the ras lockout circuit internally delays the prec harge operation until the array restore operation has been completed (t ras satisfied) so that the auto-precharge command may be issued with any read or write command. 7.7.1 burst read with auto-precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operati on on the rising edge which is (al + bl/2) cycles later from the read wi th ap command if t ras (min) and t rtp (min) are satisfied. (example timing waveform refer to 10.23 burst read operation with auto-precharge diagram in chapter 10) if t ras (min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start poin t of auto-precharge oper ation will be delayed until t rtp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where t rtp ends (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto- precharge to the next activate command becomes al + ru{ (t rtp + t rp ) / t ck(avg) } (example timing waveform refer to 10.24 burst read operation with auto-precharge diagram in chapter 10.) , for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + ru{ (t rtp + t rp ) / t ck(avg) }, where ru stands for ?rounded up to the next integer?. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. z the ras precharge time (t rp ) has been satisfied from the clock at which the auto-precharge begins. z the ras cycle time (t rc ) from the previous bank activation has been satisfied. (example timing waveforms refer to 10.25 to 10.26 burst read with auto-precharge followed by an activation to the same bank (t rc limit) and (t rp limit) diagram in chapter 10) 7.7.2 burst write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge ope ration after the completion of the burst write plus write recovery time (wr) programmed in the mode register. the bank undergoing auto- precharge from the completion of the write burst ma y be reactivated if the following two conditions are satisfied. z the data-in to bank activate delay time (wr + t rp ) has been satisfied. z the ras cycle time (t rc ) from the previous bank activation has been satisfied. (example timing waveforms refer to 10.27 to 10.28 burst write with auto-precharge (t rc limit) and (wr + t rp limit) diagram in chapter 10)
w9751g6jb publication release date: aug. 03, 2010 - 29 - revision a04 table 5 ? precharge & auto-precharge clarifications from command to command minimum delay between ?from command? to ?to command? unit notes precharge (to same bank as read) al + bl/2 + max(rtp, 2) - 2 clks 1, 2 read precharge all al + bl/2 + max(rtp, 2) - 2 clks 1, 2 precharge (to same bank as read w/ap) al + bl/2 + max(rtp, 2) - 2 clks 1, 2 read w/ap precharge all al + bl/2 + max(rtp, 2) - 2 clks 1, 2 precharge (to same bank as write) wl + bl/2 + t wr clks 2 write precharge all wl + bl/2 + t wr clks 2 precharge (to same bank as write w/ap) wl + bl/2 + wr clks 2 write w/ap precharge all wl + bl/2 + wr clks 2 precharge (to same bank as precharge) 1 clks 2 precharge precharge all 1 clks 2 precharge 1 clks 2 precharge all precharge all 1 clks 2 notes: 1. rtp[cycles] = ru{ trtp[ns] / tck(avg)[ns] }, where ru stands for round up. 2. for a given bank, the precharge period should be counted from the latest prechar ge command, either one bank precharge or precharge all, issued to that bank. the precharge period is satisfied after trp depending on the latest precharge command issued to that bank. 7.8 refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 8192 times (rows) within 64ms. the period between the auto refresh command and the next command is specified by t rfc . self refresh mode enters issuing the self refres h command (cke asserted "low") while all banks are in the idle state. the device is in self refres h mode for as long as cke held "low". in the case of 8192 burst auto refresh command s, 8192 burst auto refresh comma nds must be performed within 7.8 s before entering and after exiting the self refr esh mode. in the case of distributed auto refresh commands, distributed auto refresh commands must be issued every 7.8 s and the last distributed auto refresh commands must be performed within 7. 8 s before entering the self refresh mode. after exiting from the self refresh mode, the refresh oper ation must be performed within 7.8 s. in self refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except cke buffer). (example timing waveform refer to 10.29 self refresh diagram in chapter 10) 7.9 power down mode power-down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mo de register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge or auto-precharge or auto refresh is in progress, but power down i dd specification will not be applied until finishing those operations. the dll should be in a locked state when powe r-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation.
w9751g6jb publication release date: aug. 03, 2010 - 30 - revision a04 7.9.1 power down entry two types of power down mode can be performed on the device: precharge power down mode and active power down mode. if power down occurs when all banks are idle, this mode is referred to as precharge power down; if power down occurs when there is a row active in any bank, this mode is referred to as active power down. entering power down deactivates the input and output buffers, excluding clk, clk , odt and cke. also the dll is disabled upon entering precharge power down or slow exit active power down, but the dll is kept enabled during fast exit active power down. in power down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and odt should be in a valid state but all other input signals are ?don?t care?. cke low must be maintained until t cke has been satisfied. maximum power down duration is limited by the refresh requirements of the device, which allows a maximum of 9 x trefi if maximum posting of ref is utilized immediately before entering power down. (example timing waveforms refer to 10.30 to 10.31 active and precharged power down mode entry and exit diagram in chapter 10) 7.9.2 power down exit the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). cke high must be maintained until t cke has been satisfied. a valid, executable command can be applied with power-down exit latency, t xp , t xard , or t xards , after cke goes high. power-down exit latency is defined at ac characteristics table of this data sheet. 7.10 input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. od t must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular s peed grade. during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power down ma y be exited and dll must be reset via mrs command after precharge power down exit. depending on new clock frequency an additional mrs or emrs command may need to be issued to appropriately set the wr, cl etc? during dll re-lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. (example timing waveform refer to 10.32 clock frequency change in precharge power down mode diagram in chapter 10)
w9751g6jb publication release date: aug. 03, 2010 - 31 - revision a04 8. operation mode 8.1 command truth table cke command previous cycle current cycle ba1 ba0 a12 a11 a10 a9-a0 cs ras cas we notes bank activate h h ba row address l l h h 1,2 single bank precharge h h ba x l x l l h l 1,2 precharge all banks h h x x h x l l h l 1 write h h ba column l column l h l l 1,2,3 write with auto-precharge h h ba column h column l h l l 1,2,3 read h h ba column l column l h l h 1,2,3 read with auto-precharge h h ba column h column l h l h 1,2,3 (extended) mode register set h h ba op code l l l l 1,2 no operation h x x x x x l h h h 1 device deselect h x x x x x h x x x 1 refresh h h x x x x l l l h 1 self refresh entry h l x x x x l l l h 1,4 h x x x self refresh exit l h x x x x l h h h 1,4,5 h x x x power down mode entry h l x x x x l h h h 1,6 h x x x power down mode exit l h x x x x l h h h 1,6 notes: 1. all ddr2 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. 2. bank addresses ba[1:0] determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 3. burst reads or writes at bl = 4 can not be terminated or interrupted. see burst interrupt in section 7.5 for details. 4. v ref must be maintained during self refresh operation. 5. self refresh exit is asynchronous. 6. the power down does not perform any refresh operations. the duration of power down mode is therefore limited by the refresh requirements outlined in section 7.9.
w9751g6jb publication release date: aug. 03, 2010 - 32 - revision a04 8.2 clock enable (cke) truth table for synchronous transitions cke current state 2 previous cycle 1 (n-1) current cycle 1 (n) command (n) 3 ras , cas , we , cs action (n) 3 notes l l x maintain power down 11, 13, 15 power down l h deselect or nop power down exit 4, 8, 11, 13 l l x maintain power down 11, 15, 16 self refresh l h deselect or nop self refresh exit 4, 5, 9, 16 bank(s) active h l deselect or nop active power down entry 4, 8, 10, 11, 13 h l deselect or nop precharge power down entry 4, 8, 10, 11, 13 all banks idle h l refresh self refresh entry 6, 9, 11, 13 h h refer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; c ke (n?1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserv ed unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on every clo ck edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power down and self refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. see sect ion 7.9 "power down mode" and section 7.3.7/7.3.8 "self refresh entry/exit command" for a detailed list of restrictions. 11. tckemin of 3 clocks means cke must be registered on thre e consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 cl ocks of registration. thus, afte r any cke transition, cke may not transition from its valid leve l during the time period of t is + 2 x t ck + t ih . 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see section 7.2.4. 13. the power down does not perform any refresh operations. the duration of power down mode is therefore limited by the refresh requirements outlined in section 7.9. 14. cke must be maintained high while the sdram is in ocd calibration mode. 15. ?x? means ?don?t care (including fl oating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emr (1)). 16. v ref must be maintained during self refresh operation. 8.3 data mask (dm) truth table function dm dqs note write enable l valid 1 write inhibit h x 1 note: 1. used to mask write data, provided co incident with the corresponding data.
w9751g6jb publication release date: aug. 03, 2010 - 33 - revision a04 8.4 function truth table current state cs ras cas we address command action notes h x x x x dsl nop or power down l h h h x nop nop or power down l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act row activating l l h l ba, a10 pre/prea precharge/ precharge all banks l l l h x aref/self auto refresh or self refresh 2 idle l l l l op-code mrs/emrs mode/extended register accessing 2 h x x x x dsl nop l h h h x nop nop l h l h ba, ca, a10 read/reada begin read l h l l ba, ca, a10 writ/writa begin write l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea precharge/ precharge all banks l l l h x aref/self illegal banks active l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada burst interrupt 1,3 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal read l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa burst interrupt 1,3 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal write l l l l op-code mrs/emrs illegal
w9751g6jb publication release date: aug. 03, 2010 - 34 - revision a04 function truth table, continued current state cs ras cas we address command action notes h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal read with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal write with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop-> idle after t rp l h h h x nop nop-> idle after t rp l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea nop-> idle after t rp 1 l l l h x aref/self illegal precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop-> row active after t rcd l h h h x nop nop-> row active after t rcd l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal row activating l l l l op-code mrs/emrs illegal
w9751g6jb publication release date: aug. 03, 2010 - 35 - revision a04 function truth table, continued current state cs ras cas we address command action notes h x x x x dsl nop-> bank active after t wr l h h h x nop nop-> bank active after t wr l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa new write l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal write recovering l l l l op-code mrs/emrs illegal h x x x x dsl nop-> precharge after t wr l h h h x nop nop-> precharge after t wr l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal write recovering with auto- precharge l l l l op-code mrs/emrs illegal h x x x x dsl nop-> idle after t rc l h h h x nop nop-> idle after t rc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal refreshing l l l l op-code mrs/emrs illegal h x x x x dsl nop-> idle after t mrd l h h h x nop nop-> idle after t mrd l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal mode register accessing l l l l op-code mrs/emrs illegal notes: 1. this command may be issued for other banks, depending on the state of the banks. 2. all banks must be in "idle". 3. read or write burst interruption is pr ohibited for burst length of 4 and only allo wed for burst length of 8. burst read/writ e can only be interrupted by another read/write with 4 bit burst boundary. any other case of read/write interrupt is not allowed. remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data.
w9751g6jb publication release date: aug. 03, 2010 - 36 - revision a04 8.5 simplified stated diagram ocd calibration initialization sequence self refreshing refreshing precharge power down activating idle all banks precharged setting mr,emr (1) emr (2) emr (3) active power down bank active reading writing writing with auto-precharge precharging reading with auto-precharge (e)mrs ref self ckeh ckel ckeh act pre, prea read ckel ckeh ckel write writa writa reada write reada reada ckel autoomatic sequence command sequence read ckel pre ckel write read ckel pre, prea pre, prea writa ckel = cke low, enter power down ckeh = cke high, exit power down ckeh = cke high, exit self refresh act = activate writa = write with auto-precharge reada = read (with auto-precharge prea = precharge all (e)mrs = (extended) mode register set self = enter self refresh ref = refresh
w9751g6jb publication release date: aug. 03, 2010 - 37 - revision a04 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit notes voltage on v dd pin relative to v ss v dd -1.0 ~ 2.3 v 1, 2 voltage on v ddq pin relative to v ss v ddq -0.5 ~ 2.3 v 1, 2 voltage on v ddl pin relative to v ss v ddl -0.5 ~ 2.3 v 1, 2 voltage on any pin relative to v ss v in , v out -0.5 ~ 2.3 v 1, 2 storage temperature t stg -55 ~ 100 c 1, 2, 3 notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. when v dd and v ddq and v ddl are less than 500mv; v ref may be equal to or less than 300mv. 3. storage temperature is the case surface temperature on the center/top side of the dram. 9.2 operating temperature condition parameter symbol rating unit notes operating temperature (for -18/-25/-3) t opr 0 ~ 85 c 1, 2, 3 operating temperat ure (for 25i) t opr -40 ~ 95 c 1, 2, 3, 4 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. 2. supporting 0 ~ 85c with full jedec ac and dc specifications. 3. supporting 0 ~ 85 c and being able to extend to 95 c with doubling auto refresh commands in frequency to a 32 ms period ( t refi = 3.9 s) and to enter to self refresh mode at this high temperature range via a7 "1" on emr (2). 4. during operation, the dram case temperature must be ma intained between -40 to 95c for industrial parts under all specification parameters. 9.3 recommended dc operating conditions sym. parameter min. typ. max. unit notes v dd supply voltage 1.7 1.8 1.9 v 1 v ddl supply voltage for dll 1.7 1.8 1.9 v 5 v ddq supply voltage for out put 1.7 1.8 1.9 v 1, 5 v ref input reference voltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref - 0.04 v ref v ref + 0.04 v 4 notes: 1. there is no specific device v dd supply voltage requirement for sstl_18 comp liance. however under all conditions v ddq must than or equal to v dd . 2. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3. peak to peak ac noise on v ref may not exceed +/-2 % v ref (dc). 4. v tt of transmitting device must track v ref of receiving device. 5. v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together.
w9751g6jb publication release date: aug. 03, 2010 - 38 - revision a04 9.4 odt dc electrical characteristics parameter/condition sym. min. nom. max. unit notes rtt effective impedance value for emrs(a6,a2)=0,1; 75 ? rtt1(eff) 60 75 90 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ? rtt2(eff) 120 150 180 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ? rtt3(eff) 40 50 60 1, 2 deviation of v m with respect to v ddq /2 v m -6 +6 % 1 notes: 1. test condition for rtt measurements. 2. optional for ddr2-667, mandatory for ddr2-800 and ddr2-1066. measurement defini tion for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac) ) and i(v il (ac) ) respectively. v ih (ac) , v il (ac) , and v ddq values defined in sstl_18. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac) ? i(v ilac) ) measurement definition for v m : measure voltage (v m ) at test pin (midpoint) with no load. v m = ((2 x v m / v ddq ) ? 1) x 100% 9.5 input dc logic level parameter sym. min. max. unit dc input logic high v ih(dc) v ref + 0.125 v ddq + 0.3 v dc input logic low v il(dc) -0.3 v ref - 0.125 v 9.6 input ac logic level -18 -25/25i/-3 parameter sym. min. max. min. max. unit ac input logic high v ih (ac) v ref + 0.200 ? v ref + 0.200 v ddq + v peak 1 v ac input logic low v il (ac) ? v ref - 0.200 v ssq - v peak 1 v ref - 0.200 v note: 1. refer to the page 66 sections 9.14.1 and 9.14.2 ac overshoot/undershoot s pecification table for v peak value: maximum peak amplitude allowed for overshoot/undershoot.
w9751g6jb publication release date: aug. 03, 2010 - 39 - revision a04 9.7 capacitance sym. parameter min. max. unit c ck input capacitance , clk and clk 1.0 2.0 pf c dck input capacitance delta , clk and clk ? 0.25 pf c i input capacitance, all other input-only pins 1.0 2.0 pf c di input capacitance delta, all other input-only pins ? 0.25 pf c io input/output capacitance, dq, ldm, udm, ldqs, ldqs , udqs, udqs 2.5 3.5 pf c dio input/output capacitance delta, dq, ldm, udm, ldqs, ldqs , udqs, udqs ? 0.5 pf 9.8 leakage and output buffer characteristics sym. parameter min. max. unit notes i il input leakage current (0v Q v in Q v dd ) -2 2 a 1 i ol output leakage current (output disabled, 0v Q v out Q v ddq ) -5 5 a 2 v oh minimum required output pull-up v tt + 0.603 ? v v ol maximum required output pull-down ? v tt - 0.603 v i oh(dc) output minimum source dc current -13.4 ? ma 3, 5 i ol(dc) output minimum sink dc current 13.4 ? ma 4, 5 notes: 1. all other pins not under test = 0 v. 2. dq, ldqs, ldqs , udqs, udqs are disabled and odt is turned off. 3. v ddq = 1.7 v; v out = 1.42 v. (v out - v ddq )/i oh must be less than 21 ? for values of v out between v ddq and v ddq - 0.28v. 4. v ddq = 1.7 v; v out = 0.28v. v out /i ol must be less than 21 ? for values of v out between 0 v and 0.28v. 5. the values of i oh(dc) and iol(dc) are based on the conditions given in notes 3 and 4. they are used to test drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver.
w9751g6jb publication release date: aug. 03, 2010 - 40 - revision a04 9.9 dc characteristics -18 -25/25i -3 sym. conditions max. max. max. unit notes i dd0 operating current - one bank active-precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t rasmin(idd) ; cke is high, cs is high between valid commands; address and control inputs are switching; databus inputs are switching. 105 90 80 ma 1,2,3,4,5, 6 i dd1 operating current - one bank active-read- precharge i out = 0 ma; bl = 4, cl = cl (idd) , al = 0; t ck = t ck(idd) , t rc = t rc(idd) , t ras = t rasmin(idd) , t rcd = t rcd(idd) ; cke is high, cs is high between valid commands; address and control inputs are switching; data bus inputs are switching. 115 100 90 ma 1,2,3,4,5, 6 i dd2p precharge power-down current all banks idle; t ck = t ck(idd) ; cke is low; other control and address inputs are stable; data bus inputs are floating. (t case Q 85 c) 8 8 8 ma 1,2,3,4,5, 6,7 i dd2n precharge standby current all banks idle; t ck = t ck(idd) ; cke is high, cs is high; other control and address inputs are switching; data bus inputs are switching. 50 45 40 ma 1,2,3,4,5, 6 i dd2q precharge quiet standby current all banks idle; t ck = t ck(idd) ; cke is high, cs is high; other control and address inputs are stable; data bus inputs are floating. 40 35 35 ma 1,2,3,4,5, 6 i dd3pf fast pdn exit mrs(12) = 0 15 15 15 ma 1,2,3,4,5, 6 i dd3ps active power-down current all banks open; t ck = t ck(idd) ; cke is low; other control and address inputs are stable; data bus inputs are floating. (t case Q 85 c) slow pdn exit mrs(12) = 1 12 12 12 ma 1,2,3,4,5, 6,7 i dd3n active standby current all banks open; t ck = t ck(idd) ; t ras = t rasmax(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands; other control and address inputs are switching; data bus inputs are switching. 75 65 60 ma 1,2,3,4,5, 6
w9751g6jb publication release date: aug. 03, 2010 - 41 - revision a04 i dd4r operating burst read current all banks open, continuous burst reads, i out = 0 ma; bl = 4, cl = cl (idd), al = 0; t ck = t ck(idd) ; t ras = t rasmax(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands; address inputs are switching; data bus inputs are switching. 165 140 125 ma 1,2,3,4,5, 6 i dd4w operating burst write current all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; t ck = t ck(idd) ; t ras = t rasmax(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands; address inputs are switching; data bus inputs are switching. 200 165 150 ma 1,2,3,4,5, 6 i dd5b burst refresh current t ck = t ck(idd) ; refresh command every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address inputs are switching; data bus inputs are switching. 105 95 90 ma 1,2,3,4,5, 6 i dd6 self refresh current cke Q 0.2 v, external clock off, clk and clk at 0 v; other control and address inputs are floating; data bus inputs are floating. (t case Q 85 c) 6 6 6 ma 1,2,3,4,5, 6,7 i dd7 operating bank interleave read current all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (idd), al = t rcd(idd) - 1 x t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) , t rcd = t rcd(idd) ; cke is high, cs is high between valid commands; address bus inputs are st able during deselects; data bus inputs are switching. 245 200 180 ma 1,2,3,4,5, 6 notes: 1. v dd = 1.8 v 0.1v; v ddq = 1.8 v 0.1v. 2. i dd specifications are tested after the device is properly initialized. 3. input slew rate is specified by ac parametric test condition. 4. i dd parameters are specifi ed with odt disabled. 5. data bus consists of dq, ldm, udm, ldqs, ldqs , udqs and udqs . 6. definitions for i dd low = v in Q v il (ac) (max) high = v in R v ih (ac) (min) stable = inputs stable at a high or low level floating = inputs at v ref = v ddq /2 switching = inputs changing between high and low every ot her clock cycle (once per two clocks) for address and control signals, and inputs changing between high and lo w every other data transfer (once per clock) for dq signals not including masks or strobes. 7. the following i dd values must be derated (i dd limits increase), when t case R 85c i dd2p must be derated by 20 %; i dd3p (slow) must be derated by 30 % and i dd6 must be derated by 80 %. (i dd6 will increase by this amount if t case < 85c and the 2x refresh option is still enabled)
w9751g6jb publication release date: aug. 03, 2010 - 42 - revision a04 9.10 idd measurement test parameters speed grade ddr2-1066 (-18) ddr2-800 (-25/25i) ddr2-667 (-3) bin(cl-t rcd -t rp) 7-7-7 5-5-5/6-6-6 5-5-5 unit cl (idd) 7 5/6 5 tck t ck(idd) 1.875 2.5 3 ns t rcd(idd) 13.125 12.5 15 ns t rp(idd) 13.125 12.5 15 ns t rc(idd) 53.125 52.5 55 ns t rasmin(idd) 40 40 40 ns t rasmax(idd) 70000 70000 70000 ns t rrd(idd)-2kb 10 10 10 ns t faw(idd)-2kb 45 45 50 ns t rfc(idd) 105 105 105 ns
w9751g6jb publication release date: aug. 03, 2010 - 43 - revision a04 9.11 ac characteristics 9.11.1 ac characteristics and operat ing condition for -18 speed grade speed grade ddr2-1066 (-18) bin(cl-t rcd -t rp) 7-7-7 sym. parameter min. max. unit 25 notes t rcd active to read/write command delay time 13.125 ? ns 23 t rp precharge to active command period 13.125 ? ns 23 t rc active to ref/active command period 53.125 ? ns 23 t ras active to precharge command period 40 70000 ns 4,23 t rfc auto refresh to active/auto refresh command period 105 ? ns 5 0 c Q t case Q 85 c ? 7.8 s 5 t refi average periodic refresh interval 85 c < t case Q 95 c ? 3.9 s 5,6 t ccd cas to cas command delay 2 ? n ck t ck(avg) @ cl=4 3.75 7.5 ns 30,31 t ck(avg) @ cl=5 3 7.5 ns 30,31 t ck(avg) @ cl=6 2.5 7.5 ns 30,31 t ck(avg) average clock period t ck(avg) @ cl=7 1.875 7.5 ns 30,31 t ch(avg) average clock high pulse width 0.48 0.52 t ck(avg) 30,31 t cl(avg) average clock low pulse width 0.48 0.52 t ck(avg) 30,31 t ac dq output access time from clk/ clk -350 350 ps 35 t dqsck dqs output access time from clk / clk -325 325 ps 35 t dqsq dqs-dq skew for dqs & associated dq signals ? 175 ps 13 t cke cke minimum high and low pulse width 3 ? n ck 7 t rrd active to active command period for 2kb page size 10 ? ns 8,23 t faw four activate window for 2kb page size 45 ns 23 t wr write recovery time 15 ? ns 23 t dal auto-precharge write recovery + precharge time wr + tn rp ? n ck 24 t wtr internal write to read command delay 7.5 ? ns 9,23 t rtp internal read to precharge command delay 7.5 ? ns 4,23 t is (base) address and control input setup time 125 ? ps 10,26, 40,42,43 t ih (base) address and control input hold time 200 ? ps 11,26, 40,42,43 t is (ref) address and control input setup time 325 ? ps 10,26, 40,42,43 t ih (ref) address and control input hold time 325 ? ps 11,26, 40,42,43 t ipw address and control input pul se width for each input 0.6 ? t ck(avg) t dqss dqs latching rising transitions to associated clock edges -0.25 0.25 t ck(avg) 28 t dss dqs falling edge to clk setup time 0.2 ? t ck(avg) 28 t dsh dqs falling edge hold time from clk 0.2 ? t ck(avg) 28 t dqsh dqs input high pulse width 0.35 ? t ck(avg) t dqsl dqs input low pulse width 0.35 ? t ck(avg)
w9751g6jb publication release date: aug. 03, 2010 - 44 - revision a04 ac characteristics and operating c ondition for -18 speed grade, continued speed grade ddr2-1066 (-18) bin(cl-t rcd -t rp) 7-7-7 sym. parameter min. max. units 25 notes t wpre write preamble 0.35 ? t ck(avg) t wpst write postamble 0.4 0.6 t ck(avg) 12 t rpre read preamble 0.9 1.1 t ck(avg) 14,36 t rpst read postamble 0.4 0.6 t ck(avg) 14,37 t ds(base) dq and dm input setup time 0 ? ps 16,27,29, 41,42,44 t dh(base) dq and dm input hold time 75 ? ps 17,27,29, 41,42,44 t ds(ref) dq and dm input setup time 200 ? ps 16,27,29, 41,42,44 t dh(ref) dq and dm input hold time 200 ? ps 17,27,29, 41,42,44 t dipw dq and dm input pulse width for each input 0.35 ? t ck(avg) t hz data-out high-impedance time from clk/ clk ? t ac,max ps 15,35 t lz(dqs) dqs/ dqs -low-impedance time from clk/ clk t ac,min t ac,max ps 15,35 t lz(dq) dq low-impedance time from clk/ clk 2 x t ac,min t ac,max ps 15,35 t hp clock half pulse width min. (t ch(abs) , t cl(abs) ) ? ps 32 t qhs data hold skew factor ? 250 ps 33 t qh dq/dqs output hold time from dqs t hp - t qhs ? ps 34 t xsnr exit self refresh to a non-read command t rfc + 10 ? ns 23 t xsrd exit self refresh to a read command 200 ? n ck t xp exit precharge power down to any command 3 ? n ck t xard exit active power down to read command 3 ? n ck 18 t xards exit active power down to read command (slow exit, lower power) 10 - al ? n ck 18,19 t aond odt turn-on delay 2 2 n ck 20 t aon odt turn-on t ac,min t ac,max + 2.575 ns 20,35 t aonpd odt turn-on (power down mode) t ac,min + 2 3 x t ck(avg) + t ac,max +1 ns t aofd odt turn-off delay 2.5 2.5 n ck 21,39 t aof odt turn-off t ac,min t ac,max + 0.6 ns 21,38,39 t aofpd odt turn-off (power down mode) t ac,min + 2 2.5 x t ck(avg) + t ac,max + 1 ns t anpd odt to power down entry latency 4 ? n ck t axpd odt power down exit latency 11 n ck t mrd mode register set command cycle time 2 ? n ck t mod mrs command to odt update delay 0 12 ns 23 t oit ocd drive mode output delay 0 12 ns 23 t delay minimum time clocks remain on after cke asynchronously drops low t is +t ck(avg) +t ih ? ns 22
w9751g6jb publication release date: aug. 03, 2010 - 45 - revision a04 9.11.2 ac characteristics and operati ng condition for -25/25i/-3 speed grade speed grade ddr2-800 (-25/25i) ddr2-667 (-3) bin(cl-t rcd -t rp) 5-5-5/6-6-6 5-5-5 sym. parameter min. max. min. max. units 25 notes t rcd active to read/write command delay time 12.5 ? 15 ? ns 23 t rp precharge to active command period 12.5 ? 15 ? ns 23 t rc active to ref/active command period 52.5 ? 55 ? ns 23 t ras active to precharge command period 40 70000 40 70000 ns 4,23 t rfc auto refresh to active/auto refresh command period 105 ? 105 ? ns 5 0 c Q t case Q 85 c ? 7.8 ? 7.8 s 5 t refi average periodic refresh interval 85 c < t case Q 95 c ? 3.9 ? 3.9 s 5,6 t ccd cas to cas command delay 2 ? 2 ? n ck t ck(avg) @ cl=3 5 8 5 8 ns 30,31 t ck(avg) @ cl=4 3.75 8 3.75 8 ns 30,31 t ck(avg) @ cl=5 2.5 8 3 8 ns 30,31 t ck(avg) average clock period t ck(avg) @ cl=6 2.5 8 ? ? ns 30,31 t ch(avg) average clock high pulse width 0.48 0.52 0.48 0.52 t ck(avg) 30,31 t cl(avg) average clock low pulse width 0.48 0.52 0.48 0.52 t ck(avg) 30,31 t ac dq output access time from clk/ clk -400 400 -450 450 ps 35 t dqsck dqs output access time from clk / clk -350 350 -400 400 ps 35 t dqsq dqs-dq skew for dqs & associated dq signals ? 200 ? 240 ps 13 t cke cke minimum high and low pulse width 3 ? 3 ? n ck 7 t rrd active to active command period for 2kb page size 10 ? 10 ? ns 8,23 t faw four activate window for 2kb page size 45 ? 50 ? ns 23 t wr write recovery time 15 ? 15 ? ns 23 t dal auto-precharge write recovery + precharge time wr + tn rp ? wr + tn rp ? n ck 24 t wtr internal write to read command delay 7.5 ? 7.5 ? ns 9,23 t rtp internal read to precharge command delay 7.5 ? 7.5 ? ns 4,23 t is (base) address and control input setup time 175 ? 200 ? ps 10,26, 40,42,43 t ih (base) address and control input hold time 250 ? 275 ? ps 11,26, 40,42,43 t is (ref) address and control input setup time 375 ? 400 ? ps 10,26, 40,42,43 t ih (ref) address and control input hold time 375 ? 400 ? ps 11,26, 40,42,43 t ipw address and control input pulse width for each input 0.6 ? 0.6 ? t ck(avg) t dqss dqs latching rising trans itions to associated clock edges -0.25 0.25 -0.25 0.25 t ck(avg) 28 t dss dqs falling edge to clk setup time 0.2 ? 0.2 ? t ck(avg) 28 t dsh dqs falling edge hold time from clk 0.2 ? 0.2 ? t ck(avg) 28 t dqsh dqs input high pulse width 0.35 ? 0.35 ? t ck(avg) t dqsl dqs input low pulse width 0.35 ? 0.35 ? t ck(avg)
w9751g6jb publication release date: aug. 03, 2010 - 46 - revision a04 ac characteristics and operating conditi on for -25/25i/-3 speed grades, continued speed grade ddr2-800 (-25/25i) ddr2-667 (-3) bin(cl-t rcd -t rp) 5-5-5/6-6-6 5-5-5 sym. parameter min. max. min. max. units 25 notes t wpre write preamble 0.35 ? 0.35 ? t ck(avg) t wpst write postamble 0.4 0.6 0.4 0.6 t ck(avg) 12 t rpre read preamble 0.9 1.1 0.9 1.1 t ck(avg) 14,36 t rpst read postamble 0.4 0.6 0.4 0.6 t ck(avg) 14,37 t ds(base) dq and dm input setup time 50 ? 100 ? ps 16,27,29, 41,42,44 t dh(base) dq and dm input hold time 125 ? 175 ? ps 17,27,29, 41,42,44 t ds(ref) dq and dm input setup time 250 ? 300 ? ps 16,27,29, 41,42,44 t dh(ref) dq and dm input hold time 250 ? 300 ? ps 17,27,29, 41,42,44 t dipw dq and dm input pulse width for each input 0.35 ? 0.35 ? t ck(avg) t hz data-out high-impedance time from clk/ clk ? t ac,max ? t ac,max ps 15,35 t lz(dqs) dqs/ dqs -low-impedance time from clk/ clk t ac,min t ac,max t ac,min t ac,max ps 15,35 t lz(dq) dq low-impedance time from clk/ clk 2 x t ac,min t ac,max 2 x t ac,min t ac,max ps 15,35 t hp clock half pulse width min. (t ch(abs) , t cl(abs) ) min. (t ch(abs) , t cl(abs) ) ps 32 t qhs data hold skew factor ? 300 ? 340 ps 33 t qh dq/dqs output hold time from dqs t hp - t qhs ? t hp - t qhs ? ps 34 t xsnr exit self refresh to a non-read command t rfc + 10 ? t rfc + 10 ? ns 23 t xsrd exit self refresh to a read command 200 ? 200 ? n ck t xp exit precharge power down to any command 2 ? 2 ? n ck t xard exit active power down to read command 2 ? 2 ? n ck 18 t xards exit active power down to read command (slow exit, lower power) 8 - al ? 7 - al ? n ck 18,19 t aond odt turn-on delay 2 2 2 2 n ck 20 t aon odt turn-on t ac,min t ac,max + 0.7 t ac,min t ac,max + 0.7 ns 20,35 t aonpd odt turn-on (power down mode) t ac,min + 2 2 x t ck(avg) + t ac,max + 1 t ac,min + 2 2 x t ck(avg) + t ac,max + 1 ns t aofd odt turn-off delay 2.5 2.5 2.5 2.5 n ck 21,39 t aof odt turn-off t ac,min t ac,max + 0.6 t ac,min t ac,max + 0.6 ns 21,38,39 t aofpd odt turn-off (power down mode) t ac,min + 2 2.5 x t ck(avg) + t ac,max + 1 t ac,min + 2 2.5 x t ck(avg) + t ac,max + 1 ns t anpd odt to power down entry latency 3 ? 3 ? n ck t axpd odt power down exit latency 8 8 n ck t mrd mode register set command cycle time 2 ? 2 ? n ck t mod mrs command to odt update delay 0 12 0 12 ns 23 t oit ocd drive mode output delay 0 12 0 12 ns 23 t delay minimum time clocks remain on after cke asynchronously drops low t is +t ck(avg) + t ih ? t is +t ck(avg) + t ih ? ns 22
w9751g6jb publication release date: aug. 03, 2010 - 47 - revision a04 notes: 1. all voltages are referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc char acteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. odt is disabled for all measurements that are not odt-specific. 3. ac timing reference load: dq dqs dqs output timing reference point vtt = vddq/2 25 ? vddq dut figure 16 ? ac timing reference load 4. this is a minimum requirem ent. minimum read to precharge timing is al + bl / 2 provided that the trtp and tras(min) have been satisfied. 5. if refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. 6. this is an optional feature. for detail ed information, please refer to ?operating temperature condition? section 9.2 in this data sheet. 7. tcke min of 3 clocks means cke must be registered on thre e consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 cl ocks of registration. thus, afte r any cke transition, cke may not transition from its valid level during t he time period of tis + 2 x tck + tih. 8. a minimum of two clocks (2 *nck) is r equired irrespective of operating frequency. 9. twtr is at least two clocks (2 * nck) independent of operation frequency. 10. there are two sets of values listed for command/address input setup time: tis(base) and tis(ref). the tis(ref) value (for reference only) is equivalent to the baseli ne value of tis(base) at vref when the sl ew rate is 1.0 v/ns. the baseline value tis(base) is the jedec defined value, refe renced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the dev ice under test. see figure 17. if the comm and/address slew rate is not equal to 1.0 v/ns, then the baseline values must be derated by adding t he values from table of tis/tih derating values for ddr2-667, ddr2-800 and ddr2-1066 (page 55). clk clk t is(base) t ih(base) t is(base) t ih(base) v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss t is(ref) t ih(ref) t is(ref) t ih(ref) logic levels v ref levels figure 17 ? differential input waveform timing ? tis and tih
w9751g6jb publication release date: aug. 03, 2010 - 48 - revision a04 11. there are two sets of values listed for command/address input hold time: tih(base) and tih(ref). the tih(ref) value (for reference only) is equivalent to the baseli ne value of tih(base) at vref when the sl ew rate is 1.0 v/ns. the baseline value tih(base) is the jedec defined value, refe renced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the dev ice under test. see figure 17. if the comm and/address slew rate is not equal to 1.0 v/ns, then the baseline values must be derated by adding the values from table tis/tih derating values for ddr2-667, ddr2-800 and ddr2-1066 (page 55). 12. the maximum limit for the twpst parameter is not a devic e limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) will degrades accordingly. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variat ion of the output drivers as well as output slew rate mismatch between dqs / dqs and associated dq in any given cycle. 14. trpst end point and trpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (trpst), or begins driv ing (trpre). figure 18 shows a method to calculate these points when the device is no longer driving (trpst), or begins dr iving (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 15. thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (thz), or begins driving (tlz). figure 18 shows a method to calculate the point wh en device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the act ual voltage measurement points are not cr itical as long as the calculation is consistent. tlz(dq ) refers to tlz of the dq?s and tlz(dqs) refers to tlz of the (udqs, ldqs, udqs and ldqs ) each treated as single-ended signal. voh - x mv vtt - 2x mv vtt - x mv voh - 2x mv vol + 2x mv vol + x mv vtt + x mv vtt + 2x mv trpst end point trpre begin point thz,trpst end point = 2 x t1 - t2 tlz,trpre begin point = 2 x t1 - t2 thz t1 t2 tlz t1 t2 figure 18 ? method for calculating transitions and endpoints 16. input waveform timing tds with differential data strobe enabled mr[bit10]=0. there are two sets of values listed for dq and dm input setup time: tds(base) and tds(ref). the tds(ref) va lue (for reference only) is equi valent to the baseline value tds(base) at vref when the slew rate is 2.0 v/ns, differentia lly. the baseline value tds(base) is the jedec defined value, referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the vil(ac) level to the di fferential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs signals must be monotonic between vil(dc)max and vih(dc)min. see figure 19. if the differential dqs slew rate is not equal to 2.0 v/ns, then t he baseline values must be derat ed by adding the values from table of ddr2-667, ddr2-800 and ddr2-1066 tds/tdh derating with differential data strobe (page 60). 17. input waveform timing tdh with differential data strobe enabled mr[bit10]=0. there are two sets of values listed for dq and dm input hold time: tdh(base) and tdh(ref). the tdh(ref) val ue (for reference only) is equivalent to the baseline value tdh(base) at vref when the slew rate is 2.0 v/ns, differentia lly. the baseline value tdh(base) is the jedec defined value, referenced from the differential data strobe crosspoint to the input signal crossing at the vi h(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the vil(dc) level for a rising signal applied to t he device under test. dqs, dqs signals must be monotonic between vil(dc)max and vih(dc)min. see figure 19. if the differential dqs slew rate is not equal to 2.0 v/ns, then t he baseline values must be derat ed by adding the values from table of ddr2-667, ddr2-800 and ddr2-1066 tds/tdh derating with differential data strobe (page 60).
w9751g6jb publication release date: aug. 03, 2010 - 49 - revision a04 dqs dqs t ds(base) t dh(base) t ds(base) t dh(base) v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss t ds(ref) t dh(ref) t ds(ref) t dh(ref) logic levels v ref levels figure 19 ? differential input waveform timing ? tds and tdh 18. user can choose which active power down exit timing to use via mrs (bit 12) . txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing. 19. al = additive latency. 20. odt turn on time min is when the device leaves high impedance and odt resistance begins to tu rn on. odt turn on time max is when the odt resistance is fully on. both are measure fr om taond, which is interpreted differently per speed bin. for ddr2-667/800/1066, taond is 2 clock cycles after the clo ck edge that registered a first odt high counti ng the actual input clock edges. 21. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in hig h impedance. both are measured from taofd, which is interpret ed as 0.5 x tck(avg) [ns] af ter the second trailing clock edge counting from the clock edge that r egistered a first odt low and by c ounting the actual input clock edges. for ddr2-667/800: if tck(avg) = 3 ns is assumed, taofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by c ounting the actual input clock edges. for ddr2-1066: taofd is 0.9375 [ns] (= 0.5 x 1.875 [ns] ) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges. 22. the clock frequency is allowed to change during self refres h mode or precharge power-down mode. in case of clock frequency change during precharge power-do wn, a specific procedure is requi red as described in section 7.10. 23. for these parameters, the ddr2 sdram device is characte rized and verified to support tnparam = ru{tparam / tck(avg)}, which is in clock cy cles, assuming all input clock jitte r specifications are satisfied. examples: the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr2-667 5-5-5, of which trp = 15ns, the device will support tnrp = ru{trp / tck(avg)} = 5, i.e. as long as the input clock jitter specifications are met, precharge co mmand at tm and active command at tm+5 is valid even if (tm+5 - tm) is less than 15ns due to input clock jitter. for ddr2-1066 7-7-7, of which trp = 13.125 ns, the device will support tnrp = ru{trp / tck(avg)} = 7, i.e. as long as the input clock jit ter specifications are met, precharge command at tm and active command at tm+7 is valid even if (tm+7 - tm) is less than 13.125 ns due to input clock jitter. 24. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck(avg) [ps] }, where wr is the value programmed in the mode register set and ru stands for round up. example: for ddr2-1066 7-7-7 at tck(avg) = 1.875 ns with wr programmed to 8 nck, tdal = 8 + ru{13.125 ns / 1.875 ns} [nck] = 8 + 7 [nck] = 15 [nck].
w9751g6jb publication release date: aug. 03, 2010 - 50 - revision a04 25. new units, ?tck(avg)? and ?nck?, are introduced in ddr2-667, ddr2-800. unit ?tck(avg)? represents the actual tck( avg) of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. examples: for ddr2-667/800: txp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+2, even if (tm+2 - tm ) is 2 x tck(avg) + terr(2per),min. for ddr2-1066: txp = 3 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+3, even if (tm+3 - tm ) is 3 x tck(avg) + terr(3per),min. 26. these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respec tive clock signal (clk/ clk ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc. ), as the setup and hold are relative to the clock signal crossing that latches t he command/address. that is, these parameters should be met whether clock jitter is present or not. 27. if tds or tdh is violated, data corruption may occur and the data must be re-written with valid data before a valid read ca n be executed. 28. these parameters are measured from a data strobe signal ((l/u)dqs/ dqs ) crossing to its respective clock signal (clk/ clk ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, t hese parameters should be met whether clock jitter is present or not . 29. these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u)dqs/ dqs ) crossing.
w9751g6jb publication release date: aug. 03, 2010 - 51 - revision a04 30. input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters'. the jitter specified is a random jitter meeting a gaussian distribution. input clock-jitter specifications parameters for ddr2-667, ddr2-800 and ddr2-1066 ddr2-667 ddr2-800 ddr2-1066 parameter symbol min. max. min. max. min. max. unit clock period jitter tjit(per) -125 125 -100 100 -90 90 ps clock period jitter during dll locking peri od tjit(per,lck) -100 100 -80 80 -80 80 ps cycle to cycle clock period tjit(cc) -250 250 -200 200 -180 180 ps cycle to cycle clock period jitter during dll locking period tjit(cc,lck) -200 200 -160 160 -160 160 ps cumulative error across 2 cycles terr(2per) -175 175 -150 150 -132 132 ps cumulative error across 3 cycles terr(3per) -225 225 -175 175 -157 157 ps cumulative error across 4 cycles terr(4per) -250 250 -200 200 -175 175 ps cumulative error across 5 cycles terr(5per) -250 250 -200 200 -188 188 ps cumulative error across n cycles, n = 6 ... 10, inclusive terr(6-10per) -350 350 -300 300 -250 250 ps cumulative error across n cycles, n = 11 ... 50, inclusive terr(10-50per) -450 450 -450 450 -425 425 ps duty cycle jitter tjit(duty) -125 125 -100 100 -75 75 ps definitions: - tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window. tck ( avg ) = ? ? ? ? ? ? = n j j tck 1 / n where n = 200 - tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tch ( avg ) = ? ? ? ? ? ? = n j j tch 1 / ( n tck ( avg )) where n = 200 tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. tcl ( avg ) = ? ? ? ? ? ? = n j j tcl 1 / ( n tck ( avg )) where n = 200
w9751g6jb publication release date: aug. 03, 2010 - 52 - revision a04 - tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tc l jitter. tch jitter is the lar gest deviation of any single tch from tch(avg). tcl jitter is the largest devi ation of any single tcl from tcl(avg). tjit(duty) = min/max of {tjit(ch), tjit(cl)} where, tjit(ch) = {tchi- tch(avg) where i=1 to 200} tjit(cl) = {tcli- tcl(avg) where i=1 to 200} - tjit(per), tjit(per,lck) tjit(per) is defined as the largest devia tion of any single tck from tck(avg). tjit(per) = min/max of {tcki- tck(avg) where i=1 to 200} tjit(per) defines the singl e period jitter when the dll is already locked. tjit(per,lck) uses the same definition for singl e period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not guarant eed through final production testing. - tjit(cc), tjit(cc,lck) tjit(cc) is defined as the difference in clo ck period between two consecutive clock cycles: tjit(cc) = max of |tcki+1 ? tcki| tjit(cc) defines the cycle to cycle jit ter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guar anteed through final production testing. - terr(2per), terr (3per), terr (4per), terr (5per), terr (6-10per) and terr (11-50per) terr is defined as the cumulative error across multiple consecutive cycles from tck(avg). terr ( nper ) = ? ? ? ? ? ? ? + = 1 1 n i j j tck C n tck ( avg ) where ? ? ? ? ? ? ? ? ? ? 50per) ? r(11 for ter 50 n 11 10per) ? r(6 for ter 10 n 6 r(5per) for ter 5 = n r(4per) for ter 4 = n r(3per) for ter 3 = n r(2per) for ter 2 = n
w9751g6jb publication release date: aug. 03, 2010 - 53 - revision a04 31. these parameters are specified per t heir average values, however it is underst ood that the following relationship between the average timing and the absolute instant aneous timing holds at all ti mes. (min and max of spec values are to be used for calculations in the table below.) parameter symbol min max unit absolute clock period tck(abs) tck(avg),min + tj it(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width t ch(abs) tch(avg),min x tck(avg),min + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl( abs) tcl(avg),min x tck(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps examples: 1) for ddr2-667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 2) for ddr2-1066, tch(abs),min = ( 0.48 x 1875 ps ) - 75 ps = 825 ps 32. thp is the minimum of the absolute hal f period of the actual input clock. th p is an input parameter but not an input specification parameter. it is used in conjunction with tqhs to derive the dram out put timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the ac tual instantaneous clock high time; tcl(abs) is the minimum of the ac tual instantaneous clock low time; 33. tqhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n- channel variation of the output drivers 34. tqh = thp ? tqhs, where: thp is the minimum of the absolute half period of the actual input clock; and tqhs is the specification value under the max column. {the less half-pulse width distortion present, the larger t he tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2 -667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2 -667 sdram, the dram provides tqh of 1080 ps minimum. 3) if the system provides thp of 825 ps into a ddr 2-1066 sdram, the dram provides tqh of 575 ps minimum. 4) if the system provides thp of 900 ps into a ddr 2-1066 sdram, the dram provides tqh of 650 ps minimum. 35. when the device is operated with input cl ock jitter, this parameter needs to be derated by the actual terr(6-10per) of the input clock. (output deratings are re lative to the sdram input clock.) examples: 1) if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps and terr(6-10per),max = + 293 ps, then tdqsck,min(derated) = tdqsck,min - terr(6-10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck,max(derated) = tdqsck,max - terr(6-10per),min = 400 ps + 272 ps = + 672 ps. similarly, tlz(dq) for ddr2-667 derates to tlz( dq),min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz(dq),max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 2) if the measured jitter into a ddr2-1066 sdram has terr(6-10per),min = - 202 ps and terr(6-10per),max = + 223 ps, then tdqsck,min(derated) = tdqsck,min - terr(6-10per),max = - 300 ps - 223 ps = - 523 ps and tdqsck,max(derated) = tdqsck,max - terr(6-10per),min = 300 ps + 202 ps = + 502 ps. similarly, tlz(dq) for ddr2-1066 derates to tlz(dq ),min(derated) = - 700 ps - 223 ps = - 923 ps and tlz(dq),max(derated) = 350 ps + 202 ps = + 552 ps. (caution on the min/max usage!)
w9751g6jb publication release date: aug. 03, 2010 - 54 - revision a04 36. when the device is operated with input cl ock jitter, this parameter needs to be derated by the actual tjit(per) of the inpu t clock. (output deratings are rela tive to the sdram input clock.) examples: 1) if the measured jitter into a ddr2-667 sdram has tjit (per),min = - 72 ps and tjit(per),max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tc k(avg) - 72 ps = + 2178 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 93 ps = + 2843 ps. (caution on the min/max usage!) 2) if the measured jitter into a ddr2-1066 sdram has tj it(per),min = - 72 ps and tjit(per),max = + 63 ps, then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 1615.5 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 63 ps = + 2125.5 ps. (caution on the min/max usage!) 37. when the device is operated with input clock jitter, this param eter needs to be derated by the actual tjit(duty) of the inp ut clock. (output deratings are rela tive to the sdram input clock.) examples: 1) if the measured jitter into a ddr2-667 sdram has tjit(duty),min = - 72 ps and tjit(duty),max = + 93 ps, then trpst,min(derated) = trpst,min + tjit (duty),min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 93 ps = + 1592 ps. (caution on the min/max usage!) 2) if the measured jitter into a ddr2-1066 sdram has tjit (duty),min = - 72 ps and tjit(duty),max = + 63 ps, then trpst,min(derated) = trpst,min + tjit (duty),min = 0.4 x tck(avg) - 72 ps = + 678 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 63 ps = + 1188 ps. (caution on the min/max usage!) 38. when the device is operated with input clock jitter, this parameter needs to be derated by { -tjit(duty),max - terr(6- 10per),max } and { - tjit(duty),min - terr(6-10per),min } of the ac tual input clock. (output der atings are relative to the sdram input clock.) examples: 1) if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps, terr(6-10per),max = + 293 ps, tjit(duty),min = - 106 ps and tjit(duty),max = + 94 ps , then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (caution on the min/max usage!) 2) if the measured jitter into a ddr2-1066 sdram has terr(6-10per),min = - 202 ps, terr(6-10per),max = + 223 ps, tjit(duty),min = - 66 ps and tjit(duty),max = + 74 ps, then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6-10per),max } = - 350 ps + { - 74 ps - 223 ps} = - 647 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6-10per),min } = 950 ps + { 66 ps + 202 ps } = + 1218 ps. (caution on the min/max usage!) 39. for taofd of ddr2-667/800/1066, the 1/2 clock of nck in the 2.5 x nck assumes a tch(avg), average input clock high pulse width of 0.5 relative to tck(avg). taof,min and taof ,max should each be derated by the same amount as the actual amount of tch(avg) offset present at the dram input with respect to 0.5. example: if an input clock has a worst case tch(avg) of 0.48, the taof,min should be derated by subtracting 0.02 x tck(avg) from it, whereas if an input clock has a worst case t ch(avg) of 0.52, the taof,m ax should be derated by adding 0.02 x tck(avg) to it. therefore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [max(0.5, tch(avg),max) - 0.5] x tck(avg) or taof,min(derated) = min(tac,min, tac,mi n - [0.5 - tch(avg),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measured at the dram input balls. note that these deratings are in addition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6-10per). howev er tac values used in the equations shown above are from the timing par ameter table and are not derated. thus the final derated values for taof are; taof,min(derated_final) = taof,min(derated ) + { - tjit(duty),max - terr(6-10per),max } taof,max(derated_final) = taof,max(derated ) + { - tjit(duty),min - terr(6-10per),min } 40. timings are specified with command/ address input slew rate of 1.0 v/ns. 41. timings are specified with dqs an d dm input slew rate of 1.0v/ns. 42. timings are specified with clk/ clk differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode.
w9751g6jb publication release date: aug. 03, 2010 - 55 - revision a04 43. tis and tih (input setup and hold) derating. tis/tih derating values for ddr2-667, ddr2-800 and ddr2-1066 tis and tih derating values for ddr2-667, ddr2-800 and ddr2-1066 clk/ clk differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns command/ address slew rate (v/ns) tis tih tis tih tis tih unit 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +130 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -5 -14 +25 +16 +55 +46 ps 0.8 -13 -31 +17 -1 +47 +29 ps 0.7 -22 -54 +8 -24 +38 +6 ps 0.6 -34 -83 -4 -53 +26 -23 ps 0.5 -60 -125 -30 -95 0 -65 ps 0.4 -100 -188 -70 -158 -40 -128 ps 0.3 -168 -292 -138 -262 -108 -232 ps 0.25 -200 -375 -170 -345 -140 -315 ps 0.2 -325 -500 -295 -470 -265 -440 ps 0.15 -517 -708 -487 -678 -457 -648 ps 0.1 -1000 -1125 -970 -1095 -940 -1065 ps for all input signals the total tis (set up time) and tih (hold time) required is ca lculated by adding the data sheet tis(base) and tih(base) value to the tis and tih derating value respectively. example: tis (total setup time) = tis(base) + tis. setup (tis) nominal slew rate fo r a rising signal is defined as the slew rate between the last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossin g of vref(dc) and the first crossing of vil(ac)m ax. if the actual signal is always ear lier than the nominal slew rate line between shaded ?vref(dc) to ac region?, us e nominal slew rate for derati ng value. see figure 20 illustrati on of nominal slew rate for t is. if the actual signal is later than the nomi nal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc leve l is used for derating value. see figure 21 illustration of tange nt line for tis. hold (tih) nominal slew rate for a rising signal is defined as the slew rate between t he last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing o f vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than th e nominal slew rate line between shaded ?dc to vref(dc) region?, us e nominal slew rate for derati ng value. see figure 22 illustrati on of nominal slew rate for t ih. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(d c) level is used for derating va lue. see figure 23 illustration of tangent line for tih. although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac) . for slew rates in between the values listed in above tis/tih de rating values for ddr2-667, ddr2-800 and ddr2-1066 table, the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are veri fied by design and characterization.
w9751g6jb publication release date: aug. 03, 2010 - 56 - revision a04 clk clk t is t ih t is t ih nominal slew rate nominal slew rate v ref to ac region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr setup slew rate falling signal = v ref(dc) -v il(ac)max setup slew rate rising signal = v ih(ac)min -v ref(dc) v ref to ac region tf tr figure 20 ? illustration of nominal slew rate for t is
w9751g6jb publication release date: aug. 03, 2010 - 57 - revision a04 t is t ih t is t ih tangent line tangent line v ref to ac region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr setup slew rate falling signal = tangent line[v ref(dc) -v il(ac)max ] v ref to ac region nominal line setup slew rate rising signal = tangent line[v ih(ac)min -v ref(dc) ] nominal line clk clk tr tf figure 21 ? illustration of tangent line for t is
w9751g6jb publication release date: aug. 03, 2010 - 58 - revision a04 t is t ih t is t ih nominal slew rate nominal slew rate dc to v ref region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr hold slew rate rising signal = v ref(dc) -v il(dc)max hold slew rate falling signal = v ih(dc)min -v ref(dc) dc to v ref region clk clk tr tf figure 22 ? illustration of nominal slew rate for t ih
w9751g6jb publication release date: aug. 03, 2010 - 59 - revision a04 t is t ih t is t ih tangent line dc to v ref region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr dc to v ref region nominal line tangent line nominal line hold slew rate rising signal = tangent line[v ref(dc) -v il(ac)max ] hold slew rate falling signal = tangent line[v ih(dc)min -v ref(dc) ] clk clk tr tf figure 23 ? illustration of tangent line for t ih
w9751g6jb publication release date: aug. 03, 2010 - 60 - revision a04 44. data setup and hold time derating. ddr2-667, ddr2-800 and ddr2-1 066 tds/tdh derating with differential data strobe tds, tdh derating values for ddr2-667, ddr2-800 and ddr2-1066 (all units in ?ps?; the note applies to the entire table) dqs/ dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns dq slew rate (v/ns) tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - -10 -42 2 -30 14 -18 26 -6 38 6 - - 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 12 -53 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 for all input signals the total tds (setup time) and tdh (hold time) required is calc ulated by adding the data sheet tds(base) and tdh(base) value to the tds and tdh derating value respectively. example: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising si gnal is defined as the slew rate between t he last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossin g of vref(dc) and the first crossing of vil(ac)m ax. if the actual signal is always ear lier than the nominal slew rate line between shaded ?vref(dc) to ac region?, us e nominal slew rate for derating value. see fi gure 24 illustration of nominal slew rate for tds (differential dqs, dqs ). if the actual signal is later than the nomi nal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc leve l is used for derating value. see figure 25 illustration of tange nt line for tds (differential dqs, dqs ). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tdh) nominal slew rate for a falli ng signal is defined as the slew rate between the last crossing o f vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than th e nominal slew rate line between shaded ?dc level to vref(dc) region?, use nom inal slew rate for derating value. see figure 26 illustration of nominal slew rate for tdh (differential dqs, dqs ). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(d c) level is used for derating va lue. see figure 27 illustration of tangent line for tdh (differential dqs, dqs ). although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac) . for slew rates in between the values listed in above ddr2-667, ddr2-800 and ddr2-1066 tds/tdh derating with differential data strobe table, the derating values ma y be obtained by linear interpolation. these values are typically not subj ect to production test. they are veri fied by design and characterization.
w9751g6jb publication release date: aug. 03, 2010 - 61 - revision a04 t ds t dh t ds t dh nominal slew rate nominal slew rate v ref to ac region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr setup slew rate falling signal = v ref(dc) -v il(ac)max setup slew rate rising signal = v ih(ac)min -v ref(dc) v ref to ac region dqs dqs tr tf figure 24 ? illustration of nominal slew rate for tds (differential dqs, dqs )
w9751g6jb publication release date: aug. 03, 2010 - 62 - revision a04 dqs dqs t ds t dh t ds t dh tangent line tangent line v ref to ac region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr setup slew rate falling signal = tangent line[v ref(dc) -v il(ac)max ] v ref to ac region nominal line setup slew rate rising signal = tangent line[v ih(ac)min -v ref(dc) ] nominal line tf tr figure 25 ? illustration of tangent line for tds (differential dqs, dqs )
w9751g6jb publication release date: aug. 03, 2010 - 63 - revision a04 dqs dqs t ds t dh t ds t dh nominal slew rate nominal slew rate dc to v ref region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr hold slew rate rising signal = v ref(dc) -v il(dc)max hold slew rate falling signal = v ih(dc)min -v ref(dc) dc to v ref region tr tf figure 26 ? illustration of nominal slew rate for tdh (differential dqs, dqs )
w9751g6jb publication release date: aug. 03, 2010 - 64 - revision a04 dqs dqs t ds t dh t ds t dh tangent line dc to v ref region v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tf tr dc to v ref region nominal line tangent line nominal line hold slew rate rising signal = tangent line[v ref(dc) -v il(ac)max ] hold slew rate falling signal = tangent line [v ih(dc)min -v ref(dc) ] tf tr figure 27 ? illustration tangent lin e for tdh (differential dqs, dqs )
w9751g6jb publication release date: aug. 03, 2010 - 65 - revision a04 9.12 ac input test conditions condition symbol value unit notes input reference voltage v ref 0.5 x v ddq v 1 input signal maximum peak to peak swing v swing(max) 1.0 v 1 input signal minimum slew rate slew 1.0 v/ns 2, 3 notes: 1. input waveform timing is referenced to the input signal crossing through the vih /il(ac) level applied to the device under te st. 2. the input signal minimum slew rate is to be maintained over the range from vr ef to vih(ac) min for rising edges and the range from vref to vil(ac) max for falli ng edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the pos itive transitions and vih(ac) to vil(ac) on the negative transitions . 9.13 differential input/output ac logic levels parameter sym. min. max. unit notes ac differential input voltage v id (ac) 0.5 vddq + 0.6 v 1 ac differential cross point input voltage v ix (ac) 0.5 x vddq - 0.175 0.5 x vddq + 0.175 v 2 ac differential cross point output voltage v ox (ac) 0.5 x vddq - 0.125 0.5 x vddq + 0.125 v 3 notes: 1. vid (ac) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input signal (su ch as clk, ldqs or udqs) and vcp is t he complementary input signal (such as clk , ldqs or udqs ). the minimum value is equal to vih (ac) - vil (ac). 2. the typical value of vix (ac) is expected to be about 0.5 x vddq of the transmitting device and vix (ac) is expected to trac k variations in vddq. vix (ac) indicates the voltage at which differential input signals must cross. 3. the typical value of vox (ac) is expected to be about 0. 5 x vddq of the transmitting device and vox (ac) is expected to track variations in vddq. vox (ac) indicates the vo ltage at which differential output signals must cross. tf tr v ddq v ih(ac) min falling slew = rising slew = v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) v ref - v il(ac) max tf v ih(ac) min - v ref tr v ddq v ssq v ix or v ox v id v tr crossing point v cp figure 28 ? ac input test signal and di fferential signal levels waveform
w9751g6jb publication release date: aug. 03, 2010 - 66 - revision a04 9.14 ac overshoot / undershoot specification 9.14.1 ac overshoot / undershoot specifi cation for address and control pins: applies to a0-a12, ba0-ba1, /c s, /ras, /cas, /we, cke, odt parameter ? 18 ? 25/25i ? 3 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 v maximum peak amplitude allowed fo r undershoot area 0.5 0.5 0.5 v maximum overshoot area above v dd 0.5 0.66 0.8 v-ns maximum undershoot area below v ss 0.5 0.66 0.8 v-ns 9.14.2 ac overshoot / undershoot specification for clock, data, strobe and mask pins: applies to dq, ldqs, /ldqs, udqs , /udqs, ldm, udm, clk, /clk parameter ? 18 ? 25/25i ? 3 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 v maximum peak amplitude allowed fo r undershoot area 0.5 0.5 0.5 v maximum overshoot area above v ddq 0.19 0.23 0.23 v-ns maximum undershoot area below v ssq 0.19 0.23 0.23 v-ns maximum amplitude maximum amplitude overshoot area undershoot area v dd /v ddq volts (v) time (ns) v ss /v ssq figure 29 ? ac overshoot and undershoot definition
w9751g6jb publication release date: aug. 03, 2010 - 67 - revision a04 10. timing waveforms 10.1 command input timing clk clk t ck t ck t cl t ch t is t ih t is t ih t is t ih t is t ih t is t ih cs ras cas we a0~a12 ba0,1 refer to the command truth table 10.2 timing of the clk signals t ck t t t t v ih v ih(ac) v il(ac) v il clk clk clk clk v x v x v x v ih v il t ch t cl
w9751g6jb publication release date: aug. 03, 2010 - 68 - revision a04 10.3 odt timing for active/standby mode t1 t2 t3 t4 t5 t6 t7 clk cke internal term res. t8 odt t aofd t aond t is r tt clk t is t is v il(ac) v ih(ac) t0 t aon(max) t aof(min) t aof(max) t aon(min) 10.4 odt timing for power down mode t1 t2 t3 t4 t5 t6 t7 clk cke internal term res. t8 odt t is r tt clk t is v il(ac) v ih(ac) t0 t aonpd(max) t aofpd(min) t aofpd(max) t aonpd(min)
w9751g6jb publication release date: aug. 03, 2010 - 69 - revision a04 10.5 odt timing mode switch at entering power down mode clk t-5 t0 cke r tt t aonpd(max) t aond t aofpd(max) t aofd t anpd t is clk entering slow exit active power down mode or precharge power down mode t is t is t is t is t-4 t-3 t-2 t-1 t1 t2 v il(ac) v il(ac) v ih(ac) v ih(ac) odt odt odt odt internal term res. internal term res. internal term res. internal term res. active & standby mode timings to be applied active & standby mode timings to be applied power down mode timings to be applied power down mode timings to be applied r tt r tt r tt
w9751g6jb publication release date: aug. 03, 2010 - 70 - revision a04 10.6 odt timing mode switch at exiting power down mode clk t0 t7 t8 t9 t10 cke r tt r tt rtt r tt r tt odt active & standby mode timings to be applied power down mode timings to be applied t is clk internal term res. t axpd exiting from slow active power down mode or precharge power down mode t1 t5 t6 t is t is t is t is t aofd t aofpd(max) t aonpd(max) t aond v il(ac) v il(ac) v ih(ac) v ih(ac) internal term res. internal term res. internal term res. odt odt odt active & standby mode timings to be applied power down mode timings to be applied v ih(ac)
w9751g6jb publication release date: aug. 03, 2010 - 71 - revision a04 10.7 data output (read) timing clk dqs dq t dqsmax t dqsmax q t qh t rpst t cl t ch qq q clk dqs t qh t rpre dqs dqs 10.8 burst read operation: rl=5 (al=2, cl=3, bl=4) nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs dq's t8 nop nop nop nop dout a0 rl = 5 cl = 3 t dqsck nop dout a3 dout a1 dout a2 al = 2 posted cas read a nop nop nop nop nop nop nop nop
w9751g6jb publication release date: aug. 03, 2010 - 72 - revision a04 10.9 data input (write) timing v ih (ac) v il (ac) dddd v ih (dc) v il (dc) v ih (dc) v il (dc) dmin dmin dmin t ds v ih (ac) v il (ac) t wpre t dqsh t dqsl dqs dqs t wpst t ds t dh t dh dmin dqs dq dm dqs 10.10 burst write operation: rl =5 (al=2, cl=3, wl=4, bl=4) t0 t1 t2 t3 t4 t5 t6 t7 tn din a0 din a1 din a2 din a3 din a0 din a1 din a2 din a3 t dqss t dqss t dss t dss completion of the burst write nop nop nop nop nop nop nop posted cas write a t dqss t dsh t dqss t wr precharge clk cmd dqs dqs dqs case 1: with t dqss (max) case 2: with t dqss (min) wl = rl 1= 4 wl = rl 1= 4 t dsh dqs clk dqs dqs t wr
w9751g6jb publication release date: aug. 03, 2010 - 73 - revision a04 10.11 seamless burst read operation: rl = 5 ( al = 2, and cl = 3, bl = 4) t0 t1 t2 t5 t3 t6 t4 t7 t8 post cas read a post cas read b nop nop nop nop nop nop nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 clk clk cmd dqs dqs dq's al = 2 cl = 3 rl = 5 note: the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated. 10.12 seamless burst write operation: rl = 5 ( wl = 4, bl = 4) t0 t1 t2 t5 t3 t6 t4 t7 t8 post cas write a post cas write b nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 clk clk cmd dqs dqs dq's din b3 wl = rl - 1 = 4 note: the seamless burst write operation is supported by enabling a writ e command every other clock for bl = 4 operation, every four clocks for bl = 8 operation. th is operation is allowed regardless of same or different banks as long as the banks are activated .
w9751g6jb publication release date: aug. 03, 2010 - 74 - revision a04 10.13 burst read interrupt timi ng: rl =3 (cl=3, al=0, bl=8) nop nop nop nop read a t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b7 read b nop nop dq's 10.14 burst write interrupt timing: rl=3 (cl=3, al=0, wl=2, bl=8) write a nop nop write b nop t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 nop nop nop nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 din b4 din b5 din b6 din b7 dq's
w9751g6jb publication release date: aug. 03, 2010 - 75 - revision a04 10.15 write operation with data mask: wl=3, al=0, bl=4) dqs/ dqs dq dm v ih(ac) v ih(dc) t ds t dh t ds t dh wl + t dqss (max) t wr wl + t dqss (min) write clk cmdmand dqs/dqs dq dm dq dm case 1: min t dqss case 2: max t dqss clk dqs/dqs v il(dc) v il(ac) v ih(ac) v il(ac) v ih(dc) v il(dc) data mask timing
w9751g6jb publication release date: aug. 03, 2010 - 76 - revision a04 10.16 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=4, t rtp 2clks) precharge nop bank a activate nop nop nop post cas read a nop t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 t ras t rtp al+bl/2 clks t rp al = 1 cl = 3 rl = 4 nop dout a0 dout a1 dout a2 dout a3 dq's 10.17 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=8, t rtp 2clks) nop precharge nop nop nop nop nop nop post cas read a t0 t1 t2 t3 t4 t5 t6 t7 t8 t rtp al + bl/2 clks al = 1 cl = 3 rl = 4 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch clk/clk cmd dqs, dqs dq's
w9751g6jb publication release date: aug. 03, 2010 - 77 - revision a04 10.18 burst read operation followed by precharge: rl=5 (al=2, cl=3, bl=4, t rtp 2clks) nop nop precharge nop nop nop post cas read a bank a activate t0 t1 t2 t3 t4 t5 t6 t7 t8 t ras t rtp al + bl/2 clks t rp al = 2 cl = 3 rl = 5 dout a0 dout a1 dout a2 dout a3 nop cl = 3 clk/clk cmd dqs, dqs dq's 10.19 burst read operation followed by precharge: rl=6 (al=2, cl=4, bl=4, t rtp 2clks) dout a0 dout a1 dout a2 dout a3 nop nop nop precharge nop nop nop post cas reada bank a activate t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs dq's t8 t ras t rtp al + bl/2 clks t rp al = 2 cl = 4 rl = 6 cl = 4
w9751g6jb publication release date: aug. 03, 2010 - 78 - revision a04 10.20 burst read operation followed by precharge: rl=4 (al=0, cl=4, bl=8, t rtp > 2clks) 10.21 burst write operation followed by precharge: wl = (rl-1) = 3 nop nop nop nop nop nop nop post cas write a precharge t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs dq's t8 wl = 3 completion of the burst write din a0 din a1 din a2 din a3 t wr
w9751g6jb publication release date: aug. 03, 2010 - 79 - revision a04 10.22 burst write operation followed by precharge: wl = (rl-1) = 4 nop nop nop nop nop nop nop posted cas write a precharge a t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs dq's t9 wl = 4 completion of the burst write t wr din a0 din a1 din a2 din a3 10.23 burst read operation with auto-precharge: rl=4 (al=1, cl=3, bl=8, t rtp 2clks) nop nop nop bank a activate nop nop nop nop post cas reada t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs dq's t8 t rtp al + bl/2 clks t rp al = 1 cl = 3 rl = 4 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch t rtp precharge begins here a10 = 1
w9751g6jb publication release date: aug. 03, 2010 - 80 - revision a04 10.24 burst read operation with auto-precharge: rl=4 (al=1, cl=3, bl=4, t rtp > 2clks) nop nop bank a activate nop nop nop post cas reada nop t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 t rtp al + t rtp + t rp al = 1 cl = 3 rl = 4 nop dout a0 dout a1 dout a2 dout a3 dq's 4-bit prefetch precharge begins here t rp a10 = 1 10.25 burst read with auto-precharge followed by an activation to the same bank (t rc limit): rl=5 (al=2, cl=3, internal t rcd =3, bl=4, t rtp 2clks) nop nop nop nop nop nop post cas reada bank a activate t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 t ras min. (al + bl/2) al = 2 cl = 3 rl = 5 nop dout a0 dout a1 dout a2 dout a3 dq's auto-precharge begins a10 = 1 t rp t rc min.
w9751g6jb publication release date: aug. 03, 2010 - 81 - revision a04 10.26 burst read with auto-precharge followed by an activation to the same bank (t rp limit): rl=5 (al=2, cl=3, internal t rcd =3, bl=4, t rtp 2clks) nop nop nop nop nop nop post cas reada bank a activate t0 t1 t2 t3 t4 t5 t6 t7 clk/clk cmd dqs, dqs t8 t ras min. al = 2 cl = 3 rl = 5 nop dout a0 dout a1 dout a2 dout a3 dq's auto-precharge begins a10 = 1 t rp min. t rc 10.27 burst write with auto-precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 t rc min. wl= rl- 1 = 2 wr t rp nop nop nop nop nop nop nop post cas wra bank a bank a activate t0 t1 t2 t3 t4 t5 t6 t7 auto-precharge begins a10 = 1 clk/clk cmd dqs, dqs dq's completion of the burst write tm din a0 din a1 din a2 din a3
w9751g6jb publication release date: aug. 03, 2010 - 82 - revision a04 10.28 burst write with auto-precharge (wr + t rp limit): wl=4, wr=2, bl=4, t rp =3 10.29 self refresh timing t0 t1 t2 t3 t4 t5 t6 tm tn self refresh nop non-read command nop t xsnr t xsrd t ih t ih tis t ih t ih t is t is t rp t is t aofd t ck t ch t cl v il(ac) v ih(ac) v il(ac) v ih(ac) v il(dc) v ih(dc) clk cmd cke odt clk v il(ac) read command
w9751g6jb publication release date: aug. 03, 2010 - 83 - revision a04 10.30 active power down mode entry and exit timing clk clk t0 t1 t2 tn tn+1 tn+2 valid command nop nop nop nop activate t xard or t xards active power down exit active power down entry t is cke cmd t is 10.31 precharged power down mode entry and exit timing clk clk cmd t0 t1 t2 t3 tn cke tn+1 tn+2 nop nop t is t rp precharge power down entry precharge power down exit t xp t is nop nop nop nop precharge valid command
w9751g6jb publication release date: aug. 03, 2010 - 84 - revision a04 10.32 clock frequency change in precharge power down mode nop nop nop nop nop valid t0 t1 t2 t4 t x t x+1 t y t y+1 t y+2 t y+3 t y+4 t z clk t is dll reset minimum 2 clocks required before changing frequency stable new clock before power down exit frequency change occurs here 200 clocks odt is off during dll reset clk cmd cke odt t is t ih t rp t aofd t xp
w9751g6jb publication release date: aug. 03, 2010 - 85 - revision a04 11. package specification package outline wbga-84 (8x12.5 mm 2 ) 1 84x b a1 a seating plane symbol dimension (mm) min. nom. max. a a1 b d e d1 e1 ee ed aaa bbb ccc --- --- --- --- 0.10 0.20 --- --- 0.15 0.80 bsc. 0.80 bsc. 6.40 bsc. 11.20 bsc. 1.20 0.40 0.50 12.60 8.10 8.00 12.50 7.90 12.40 0.40 0.25 d ee e1 ed d1 4x 2 3 7 8 9 e --- --- --- --- a b c d e f g h j k l m n p r c ccc c a c aaa b c bbb // pin a1 index pin a1 index ball land ball opening note: 1. ball land : 0.5mm 2. ball opening : 0.4mm 3. pcb ball land suggested 0.4mm solder ball diameter refers. to post reflow condition. the window-side encapsulant
w9751g6jb publication release date: aug. 03, 2010 - 86 - revision a04 12. revision history version date page description a01 feb. 04, 2010 all initial formal data sheet a02 mar. 10, 2010 4, 5, 37, 38, 40~42, 45, 46, 65, 66 added ddr2-800, industrial parts: w9751g6jb25i and automotive parts: w9751g6jb25a a03 jun. 18, 2010 5, 40, 41 update dc characteristics i dd x current value a04 aug. 03, 2010 4, 5, 37, 38, 40~42, 45, 46, 66 removed 25a speed grade important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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